Emi Offset Register (Eor) - Motorola DSP56009 User Manual

External Memory Interface
EMI Programming Model
4.2.3

EMI Offset Register (EOR)

The EMI uses the read/write 24-bit EMI Offset Register (EOR) to calculate the
address (in external memory) of the word to be accessed during read operations. The
EOR is a single 24-bit register that is mapped to two different memory locations
(EOR0 and EOR1). The address is formed by subtracting the contents of the EOR
from the contents of EBARx. The offset is stored in 24-bit unsigned integer format.
The EOR contains a displacement value (from the start of the data-delay buffer) and
is used to access delayed data samples. For example, assuming that EBARx points to
the sample at time 0, then to read the data sample delayed by N, the value of N is
written into the EOR. The EOR has two addresses: $XFFE9 (EOR0) and $XFFED
(EOR1). When the ECSR EMI Read Trigger Select (ERTS) bit (see Figure 4-2 ) is
cleared, writing to EOR0 triggers an EMI memory read operation that will use the
value in the EOR and the value in the EBAR0 for address calculation. Writing to
EOR1 when the ERTS bit is cleared triggers an EMI memory read operation that will
use the values in the EOR and the EBAR1 for address calculation. The EOR is cleared
by hardware reset and software reset. See Section 4.2.5 EMI Data Read Register
(EDRR) on page 4-9 for a description of operation when the ERTS bit is set.
11 10 9 8
EMWIE EIS1 EIS0 EINW
23 22 21 20
EME ESTM3 ESTM2 ESTM1
Figure 4-2 EMI Control/Status Register (ECSR)
4-8
7 6 5 4
EINR EAM3 EAM2 EAM1
19 18 17 16
ESTM0 EDTM ERTS EWL2
DSP56009 User's Manual
3 2 1 0
EAM0 EWL1 EWL0 EBW
15 14 13 12
EBSY EBDF EDRF EDWE
EMI Data Bus Width
EMI Data Word Length
EMI Addressing Mode
Increment EBAR (Read)
Increment EBAR (Write)
Read/Write Interrupt Select
Memory-Wrap Interrupt Enable
EDWR Empty
EDRR Full
EDRB & EDRR Full
EMI Busy Status
EMI Data Word Length
EMI Read Trigger Select
EMI DRAM Timing
EMI SRAM Timing
EMI Enable
AA0402
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