Interrupting Sequential Rep Instructions - Motorola DSP56000 Manual

24-bit digital signal processor
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INTERRUPT
REJECTED
INTERRUPT
PENDING
INTERRUPT
INTERRUPT
REJECTED
PENDING
INTERRUPT
REJECTED
INTERRUPT
PENDING
INTERRUPT
PENDING
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
REP n2
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i
= INTERRUPT
ii
= INTERRUPT INSTRUCTION WORD
n = NORMAL INSTRUCTION WORD
i% = INTERRUPT REJECTED
Figure 7-14 Interrupting Sequential REP Instructions
MOTOROLA
RESET PROCESSING STATE
MAIN
PROGRAM
FETCHES
REP m
n1
n2
REP m
n3
n4
REP m
n5
n6
n7
n8
n9
(a) Instruction Fetches from Memory
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
i
i%
REP
n4
REP NOP
n2
n2
n2
REP NOP
REP NOP
n2
n2
n2
1
2
3
4
5
6
7
(b) Program Controller Pipeline
PROCESSING STATES
REPEAT m
TIMES
• •
n2
n2
ii1
ii2
REP
n6
n7
n4
n4
n4
REP NOP n6
REP
NOP
n4
n4
n4
REP NOP n6
8
9
10
11
12
13
n2
REPEAT m
TIMES
n4
• • •
n4
n4
REPEAT m TIMES
n6
• • •
n6
n6
INTERRUPTS RE-ENABLED
i
i
n8
ii1
ii2
n9
n6
n6
n7
n8
ii1
ii2
n6
n6
n7
n8
ii1
14
15
16
17
18
19
20
7 - 35
n9
ii2
n9
21
22

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