C Bus Control Register 1 Ch. N (Ibcr1N) - Fujitsu 8FX Hardware Manual

MB95630H Series
2
24.7.2 I

C Bus Control Register 1 ch. n (IBCR1n)

2
The I C bus control register 1 ch. n (IBCR1n) controls the following functions:
bus error interrupt, START condition generation, master/slave mode selection,
data acknowledge, general call acknowledge and transfer completion interrupt.
■ Register Configuration
bit 7
Field BER
Attribute R/W
Initial value 0
■ Register Functions
[bit7] BER: Bus error interrupt request flag bit
This bit detects the bus error.
When this bit and the BEIE bit are both set to "1", a bus error interrupt is generated.
This bit is set to "1" when an invalid START condition or an invalid STOP condition is detected.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
When this bit is set to "1", the ICCRn:EN bit is set to "0", and the I
data transfer is terminated.
bit7
Reading "0"
Reading "1"
Writing "0"
Writing "1"
[bit6] BEIE: Bus error interrupt enable bit
This bit enables or disables the bus error interrupt.
When this bit and the BER bit are both set to "1", a bus error interrupt request is generated.
bit6
Writing "0"
Writing "1"
MN702-00009-2v0-E
6 5
BEIE SCC
R/W R/W
0 0
Indicates that no bus error has been detected.
Indicates that an invalid START condition or an invalid STOP condition has been detected.
Clears this bit.
Has no effect on operation.
Disables the bus error interrupt.
Enables the bus error interrupt.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 24 I
4 3
MSS DACKE GACKE
R/W R/W
0 0
2
C bus interface operation is disabled and
Details
Details
2
C BUS INTERFACE
24.7 Registers
2 1
INTE
R/W R/W
0 0
0
INT
R/W
0
517