Fujitsu 8FX Hardware Manual page 393

MB95630H Series
[bit2:0] MOD[2:0]: Operating mode select bits
These bits set the operating conditions of the 16-bit reload timer.
• Internal clock mode (CSL[2:0] = any value between 0b000 and 0b110 inclusive)
Select the input pin function with the MOD2 bit.
When the MOD2 bit is "0",
- The TIn pin functions as a trigger input pin.
- Select the edge to be detected using the MOD[1:0] bits.
- When the edge selected in MOD[1:0] is detected, the value set to the 16-bit reload timer reload register
(upper/lower) ch. n (TMRLRHn/TMRLRLn) is reloaded to the 16-bit reload timer timer register
(upper/lower) ch. n (TMRHn/TMRLn), and the 16-bit reload counter starts counting using
TMRHn/TMRLn.
When the MOD2 bit is "1",
- The TIn pin functions as a gate input pin.
- The setting of the MOD1 bit is invalid.
- Select the valid signal level ("H" or "L") with the MOD0 bit. The 16-bit reload timer counts using
TMRHn/TMRLn only while the valid signal level is being input.
Note: When the MOD[2:0] bits are "0b000", external pin input becomes invalid. In this case, use the TRG
bit to start the 16-bit reload timer by using the software.
bit2:0
Writing "000"
Writing "001"
Writing "010"
Writing "011"
Writing "100"
Writing "101"
Writing "110"
Writing "111"
• Event count mode (CSL[2:0] = 0b111)
- The MOD2 bit is always set to "0".
- The external event clock is input from the TIn pin.
- Select the edge to be detected using the MOD[1:0] bits.
bit2:0
Writing "000"
Writing "001"
Writing "010"
Writing "011"
Writing "100"
Writing "101"
Writing "110"
Writing "111"
MN702-00009-2v0-E
TIn pin function
External pin input invalid
Trigger input
Gate input
TIn pin function
External pin input invalid
Trigger input
Setting prohibited
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 20 16-BIT RELOAD TIMER
Details (Internal clock mode)
Rising edge
Falling edge
Both edges
"L" level
"H" level
"L" level
"H" level
Details (Event count mode)
Rising edge
Falling edge
Both edges
20.7 Registers
Valid edge/level
—
Valid edge/level
—
371