Fujitsu 8FX Hardware Manual page 497

MB95630H Series
When the use of the external clock signal has been set, serial data transmission starts at the fall
of the first serial clock signal after the transmission process is started.
A transmission completion interrupt occurs the moment the TDRE bit is set to "1" when the
transmit interrupt enable bit (TIE) contains "1". At this time, the next piece of transmit data can
be written to the TDRn register. Serial transmission can be continued with the TXE bit set to
"1".
To use a transmission completion interrupt to detect the completion of serial transmission,
enable transmission completion interrupt output this way: TEIE = 0, TCIE = 1. Upon
completion of transmission, the transmission completion flag bit (SSRn:TCPL) is set to "1" and
a transmission completion interrupt occurs.
Figure 22.6-15 8-bit Transmission in Synchronous Clock Mode
Writing
to TDRn
UCKn
UIn
TDRE
TCPL
● Concurrent transmission and reception
<When external clock is enabled>
Transmission and reception can be performed independently of each other. Transmission and
reception can therefore be performed at the same time or even when their phases are shifted
from each other and overlapping.
<When internal clock is enabled>
As the transmitting side generates a serial clock, reception is influenced.
If transmission stops during reception, the receiving side is suspended. It resumes reception
when the transmitting side is restarted.
See "22.4 Pins" for operation with serial clock output and operation with serial clock input.
MN702-00009-2v0-E
D0 D1 D2 D3 D4 D5 D6 D7
Interrupt After falling of UCKn
to interrupt when external clock
controller is enabled.
FUJITSU SEMICONDUCTOR LIMITED
22.6 Operations and Setting Procedure Example
Interrupt After last 1-bit cycle
to interrupt when internal clock
controller is enabled.
CHAPTER 22 UART/SIO
475