Fujitsu 8FX Hardware Manual page 57

MB95630H Series
[bit3] SOSCE: Subclock oscillation enable bit
This bit enables or disables the subclock oscillation.
When SCS[2:0] are set to "0b000", this bit is automatically set to "1".
When SCS[2:0] or SCM[2:0] are set to "0b000", writing "0" to this bit has no effect on operation.
bit3
Writing "0"
Writing "1"
[bit2] MOSCE: Main clock oscillation enable bit
This bit enables or disables the main clock oscillation.
When SCS[2:0] are set to "0b010", this bit is automatically set to "1".
When SCS[2:0] or SCM[2:0] are set to "0b010", writing "0" to this bit has no effect on operation.
This bit is automatically set to "0" when the clock mode is changed from one mode to another mode other
than main clock mode.
When the current clock mode is subclock mode or sub-CR clock mode, writing "1" to this bit has no effect on
operation.
bit2
Writing "0"
Writing "1"
[bit1] SCRE: Sub-CR clock oscillation enable bit
This bit enables or disables the sub-CR clock oscillation.
When SCS[2:0] are set to "0b100", this bit is automatically set to "1".
When SCS[2:0] or SCM[2:0] are set to "0b100", writing "0" to this bit has no effect on operation.
When SCS[2:0] and SCM[2:0] are not set to "0b100", this bit can be modified independently of other bits.
bit1
Writing "0"
Writing "1"
[bit0] MCRE: Main CR clock oscillation enable bit
This bit enables or disables the main CR clock oscillation.
When SCS[2:0] are set to "0b110" or "0b111", this bit is automatically set to "1".
When SCS[2:0] or SCM[2:0] are set to "0b110" or "0b111", writing "0" to this bit has no effect on operation.
This bit is automatically set to "0" when the clock mode is changed from one mode to another mode except
main CR clock mode or from main CR PLL clock mode.
When the current clock mode is subclock mode or sub-CR clock mode, writing "1" to this bit has no effect on
operation.
bit0
Writing "0"
Writing "1"
MN702-00009-2v0-E
Disables the subclock oscillation.
Enables the subclock oscillation.
Disables the main clock oscillation.
Enables the main clock oscillation.
Disables the sub-CR clock oscillation.
Enables the sub-CR clock oscillation.
Disables the main CR clock oscillation.
Enables the main CR clock oscillation.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 3 CLOCK CONTROLLER
Details
Details
Details
Details
3.3 Registers
35