Fujitsu 8FX Hardware Manual page 53

MB95630H Series
[bit3:0] MWT[3:0]: Main clock oscillation stabilization wait time select bits
These bits select the main clock oscillation stabilization wait time.
bit3:0
Writing "1111"
Writing "1110"
Writing "1101"
Writing "1100"
Writing "1011"
Writing "1010"
Writing "1001"
Writing "1000"
Writing "0111"
Writing "0110"
Writing "0101"
Writing "0100"
Writing "0011"
Writing "0010"
Writing "0001"
Writing "0000"
The number of cycles in the above table is the minimum value. The maximum value is the number of cycles
in the above table plus 1/F
Note: Do not modify these bits during main clock oscillation stabilization wait time. Modify them when the
main clock oscillation stabilization bit in the system clock control register 2 (SYCC2:MRDY) has
been set to "1". These bits can be modified when the main clock is stopped with the main clock
oscillation stop bit in the system clock control register 2 (SYCC2:MOSCE) set to "0" in main CR
clock mode, main CR PLL clock mode, subclock mode, or sub-CR clock mode.
MN702-00009-2v0-E
No. of cycles
14
14
(2 - 2)/F
2 - 2
13
13
(2 - 2)/F
2 - 2
12
12
(2 - 2)/F
2 - 2
11
11
(2 - 2)/F
2 - 2
10
10
(2 - 2)/F
2 - 2
9
9
(2 - 2)/F
2 - 2
8
8
(2 - 2)/F
2 - 2
7
7
(2 - 2)/F
2 - 2
6
6
(2 - 2)/F
2 - 2
5
5
(2 - 2)/F
2 - 2
4
4
(2 - 2)/F
2 - 2
3
3
(2 - 2)/F
2 - 2
2
2
(2 - 2)/F
2 - 2
1
1
(2 - 2)/F
2 - 2
1
1
(2 - 2)/F
2 - 2
1
1
(2 - 2)/F
2 - 2
.
CH
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 3 CLOCK CONTROLLER
Details
Main clock (F
CH
CH
CH
CH
CH
CH
CH
CH
CH
CH
CH
CH
CH
CH
CH
CH
3.3 Registers
) = 4 MHz
CH
About 4.10 ms
About 2.05 ms
About 1.02 ms
About 511.5 µs
About 255.5 µs
About 127.5 µs
About 63.5 µs
About 31.5 µs
About 15.5 µs
About 7.5 µs
About 3.5 µs
About 1.5 µs
About 0.5 µs
0.0 µs
0.0 µs
0.0 µs
31