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2
CHAPTER 24 I
C BUS INTERFACE
24.2 Configuration
■ Block Diagram of I
ICCRn
DMBP
IBSRn
IBCR1n
DACKE
GACKE
IBSRn
IBCR0n
496
2
C Bus Interface
Figure 24.2-1 Block Diagram of I
Clock divider 1
5
6
7
EN
Clock selector 1
CS4
CS3
Clock divider 2
CS2
CS1
4
8
22
38
CS0
Clock selector 2
BB
Bus busy
Repeat start
RSC
Start/stop condition
Last bit
LRB
detection circuit
Transmit/receive
TRX
FBT
Arbitration lost detection circuit
BER
BEIE
INTE
INT
End
Start
SCC
Master
ACK enable
MSS
GC-ACK enable
Address ACK enable
INT timing select
Slave
AAS
GCA
General
call
AACKX
INTS
ALF
ALE
SPF
SPE
WUF
WUE
FUJITSU SEMICONDUCTOR LIMITED
2
C Bus Interface
2
I C bus interface enable
Machine clock
8
Sync
98 128
256 512
Shift clock edge
Error
First byte
Transfer interrupt
Start/stop condition
generation circuit
IDDRn register
Slave address
comparison circuit
IAARn register
Stop interrupt
MB95630H Series
Shift clock
generator
SCLn line
SDAn line
MN702-00009-2v0-E
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