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MB95630H Series
18.2
Configuration
This section shows the block diagram of the 8/16-bit PPG.
■ Block Diagram of 8/16-bit PPG
Figure 18.2-1 shows the block diagram of the 8/16-bit PPG.
CKS02
CKS01
1 MCLK
MCLK/2
MCLK/4
MCLK/8
Prescaler
MCLK/16
MCLK/32
7
F
/2
or F
/2
CH
CRH
8
F
/2
or F
/2
CH
CRH
PEN00
CKS12
CKS11
1 MCLK
MCLK/2
MCLK/4
MCLK/8
Prescaler
MCLK/16
MCLK/32
7
F
/2
or F
/2
CH
CRH
8
F
/2
or F
/2
CH
CRH
PEN01
MN702-00009-2v0-E
Figure 18.2-1 Block Diagram of 8/16-bit PPG
CKS00
Cycle setup register
01
CL K
00
6
6
or F
/2
MCRPLL
10
7
7
or F
/2
MCRPLL
11
STOP
Edge
START
detection
MD1
Used as the select signal of each selector
Cycle setup register
CKS10
Cycle setup
buffer register
1
CL K
0
6
6
or F
/2
MCRPLL
7
7
or F
/2
MCRPLL
1
STOP
0
Edge
1
START
detection
0
FUJITSU SEMICONDUCTOR LIMITED
Duty setup register
Duty setup buffer register
Compa-
LOAD
8-bit downcounter
(PPG timer n0)
BORROW
0
1
MD0
Duty setup register
Duty register buffer
cycle setup
1
0
Compa-
LOAD
circuit
8-bit downcounter
(PPG timer n1)
BORROW
CHAPTER 18 8/16-BIT PPG
18.2 Configuration
PPG timer n0
rator
circuit
REV00
0
S Q
1
R
0
1
PIE0
PUF0
POEN0
Edge
rator
detection
1
REV01
S Q
0
R
PIE1
PUF1
POEN1
Pin
PPGn0
POEN0
IRQXX
PPG timer n1
Pin
PPGn1
POEN1
IRQXX
307
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