Configuration - Fujitsu 8FX Hardware Manual

MB95630H Series
22.2

Configuration

The UART/SIO consists of the following blocks:
• UART/SIO serial mode control register 1 ch. n (SMC1n)
• UART/SIO serial mode control register 2 ch. n (SMC2n)
• UART/SIO serial status and data register ch. n (SSRn)
• UART/SIO serial input data register ch. n (RDRn)
• UART/SIO serial output data register ch. n (TDRn)
The number of pins and that of channels of the UART/SIO vary among products. For details,
refer to the device data sheet.
In this chapter, "n" in a pin name and a register abbreviation represents the channel number.
For details of pin names, register names and register abbreviations of a product, refer to the
device data sheet.
■ Block Diagram of UART/SIO
Dedicated baud rate generator
External clock input
Pin
UCKn
Serial clock output
Serial data input
Pin
UIn
Data sample clock input
Serial data output
Pin
UOn
Port control
MN702-00009-2v0-E
Figure 22.2-1 Block Diagram of UART/SIO
Clock
1/4
selector
Start Recep-
Parity
bit tion bit
operation
detection count
Shift
register
for trans-
Transmis-
Parity
mission
sion bit
operation
count
FUJITSU SEMICONDUCTOR LIMITED
PER
Reception
OVE
state
State from
decision FER
each block
circuit
RDRF
RIE
TDRE
State from
Transmis-
TEIE
each block
sion state
decision TCPL
circuit
TCIE
UART/SIO
serial status
and data
register ch. n
Shift
UART/SIO
register
serial input data
for
register ch. n
reception
UART/SIO
serial output
data register
ch. n
UART/SIO
serial mode
control
Set to
registers 1, 2
each block ch. n
CHAPTER 22 UART/SIO
22.2 Configuration
Reception
interrupt
Transmission
interrupt
457