16-Bit Reload Timer Reload Register (Upper/Lower) Ch. N (Tmrlrhn/Tmrlrln) - Fujitsu 8FX Hardware Manual

MB95630H Series
20.7.4 16-bit Reload Timer Reload Register
(Upper/Lower) ch. n (TMRLRHn/TMRLRLn)
The 16-bit reload timer reload register (upper/lower) ch. n (TMRLRHn/TMRLRLn)
sets the reload value for the 16-bit downcounter. The value written to this
register is reloaded to the 16-bit downcounter for downcounting.
■ Register Configuration
TMRLRHn
bit 7
Field D15
Attribute R/W
Initial value 0
TMRLRLn
bit 7
Field D7
Attribute R/W
Initial value 0
■ Register Functions
The 16-bit reload timer reload register ch. n sets the reload value to be reloaded to the 16-bit
downcounter.
The value set to the 16-bit reload timer reload register ch. n is reloaded to the 16-bit
downcounter for downcounting when the 16-bit reload timer starts or when an underflow
occurs. In addition, the value of this register can be modified during the counting operation of
the 16-bit reload timer.
Notes:
• A value can be written to this register even during the counting operation of the 16-bit
reload timer. To write a value to this register, use a word transfer instruction, or write
the upper byte of this register first and then its lower byte. The 16-bit reload timer
reload register ch. n has a circuit configured so that the upper byte value becomes
valid when a value is written to the lower byte.
• This register is write-only and located at the same address as the 16-bit reload timer
timer register ch. n. Therefore, a read access to this register becomes a read access
to the 16-bit reload timer timer register ch. n.
MN702-00009-2v0-E
6 5
D14 D13
R/W R/W
0 0
6 5
D6 D5
R/W R/W
0 0
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 20 16-BIT RELOAD TIMER
4 3
D12 D11
R/W R/W
0 0
4 3
D4 D3
R/W R/W
0 0
20.7 Registers
2 1
D10 D9
R/W R/W
0 0
2 1
D2 D1
R/W R/W
0 0
0
D8
R/W
0
0
D0
R/W
0
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