Fujitsu 8FX Hardware Manual page 173

MB95630H Series
Figure 11.9-2 Operation Diagram of PWM Timer Function (Fixed-cycle Mode)
Tn0DR/Tn1DR register value: "0x00" (duty ratio = 0%)
Tn0DR/Tn1DR register value: "0x80" (duty ratio = 50%)
Tn0DR/Tn1DR register value: "0xFF" (duty ratio = 99.6%)
Note: When the PWM function has been selected, the timer output pin holds the level at the point when the counter stops
(Tn0CR1/Tn1CR1:STA = 0).
MN702-00009-2v0-E
Counter value 0x00
"H"
PWM waveform
"L"
0x00
Counter value
"H"
PWM waveform
"L"
Counter value 0x00
"H"
PWM waveform
"L"
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 11 8/16-BIT COMPOSITE TIMER
11.9 Operation of PWM Timer Function
0xFF 0x00
0x80 0xFF 0x00
0xFF 0x00
(Fixed-cycle Mode)
One count width
151