16-Bit Mpg Timer Buffer Register (Upper/Lower) (Tmbur/Tmblr) - Fujitsu 8FX Hardware Manual

CHAPTER 21 MULTI-PULSE GENERATOR
21.6 Registers
21.6.7 16-bit MPG Timer Buffer Register (Upper/Lower)
(TMBUR/TMBLR)
The timer buffer register (upper/lower) (TMBUR/TMBLR) consists of two 8-bit
registers used to read the counter value of 16-bit timer.
The 16-bit MPG timer buffer register (upper) (TMBUR) and the 16-bit MPG timer buffer
register (lower) (TMBLR) store the counter value of the 16-bit timer at the point at which a
write timing trigger or a position detection trigger is generated. The counter is cleared to
"0x0000" upon the generation of the trigger.
Always use one of the following methods to access this register.
• Use the "MOVW" instruction (use a 16-bit access instruction to read the TMBUR register
address).
• Use the "MOV" instruction to read or write TMBUR first and then TMBLR.
■ Register Configuration
TMBUR
bit 7
Field T15
Attribute R
Initial value X
TMBLR
bit 7
Field T07
Attribute R
Initial value X
446
6 5
T14 T13
R R
X X
6 5
T06 T05
R R
X X
FUJITSU SEMICONDUCTOR LIMITED
4 3
T12 T11
R R
X X
4 3
T04 T03
R R
X X
MB95630H Series
2 1
T10 T09
R R
X X
2 1
T02 T01
R R
X X
MN702-00009-2v0-E
0
T08
R
X
0
T00
R
X