Notes On Using Time-Base Timer - Fujitsu 8FX Hardware Manual

CHAPTER 7 TIME-BASE TIMER

7.6 Notes on Using Time-base Timer

7.6 Notes on Using Time-base Timer
This section provides notes on using the time-base timer.
■ Notes on Using Time-base Timer
● When setting the timer by program
The timer cannot return from interrupt processing when the time-base timer interrupt request
flag bit (TBTC:TBIF) is set to "1" and the interrupt request enable bit is enabled
(TBTC:TBIE = 1). Always clear the TBIF bit in the interrupt service routine.
● Clearing Time-base Timer
The time-base timer is cleared not only by the time-base timer clear bit (TBTC:TCLR = 1) but
also when the oscillation stabilization wait time of the main clock, the main CR clock, or the
main CR PLL clock is required. When the time-base timer is selected as the count clock of the
software watchdog timer (WDTC:CS[1:0] = 0b00 or 0b01), clearing the time-base timer also
clears the software watchdog timer.
● Peripheral functions receiving clock from time-base timer
In the mode where the source oscillation of the main clock is stopped, the counter is cleared
and the time-base timer stops operating. In addition, if the counter of the time-base timer is
cleared with the output of the time-base timer being used in other peripheral functions, that will
affect the operations of such peripheral operations such as the changing of their operating
cycles.
After the counter of the time-base timer is cleared, the clock that is output from the time-base
timer for the software watchdog timer returns to the initial state. However, since the software
watchdog timer counter is also cleared at the same time as the clock for the software watchdog
timer returns to the initial state, the software watchdog timer operates in its normal cycle.
98 FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
MN702-00009-2v0-E