Operation Of Dtti Input Control - Fujitsu 8FX Hardware Manual

8-bit microcontroller new 8fx family
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MB95630H Series
21.5.5

Operation of DTTI Input Control

This section describes the operation of the DTTI input control circuit.
■ Operation of DTTI Input Control
The DTTI circuit controls the output of the value of PDRx (port x data register) to the pin
OPTx which is multiplexed with the port x where OPTx is enable by setting OPEx = 1. The
operation mode is enabled by the DTIE bit in the 16-bit MPG output control register (upper)
(OPCUR).
Note:
Before the DTTI circuit is in effect, make sure that the port x which is multiplexed with the
OPTx is configured as an output port by setting its port direction register.
When the DTIE bit in the 16-bit MPG output control register (upper) (OPCUR) is set to "1",
the waveform output at OPT5 to OPT0 pins are enabled by the valid level of the DTTI pin.
When the low input level is placed at the DTTI pin, the output of OPTx is fixed at the inactive
level. The software can set the inactive level for each OPTX pin in PDRx of port x, the OPTx
pin is then driven by the data written in the PDRx of port x.
Even while the output is fixed at the inactive level by the input of the DTTI pin, the timer
keeps running, the position detection function does not stop and the data transfer from the 16-
bit MPG output data buffer register (upper/lower) (OPDBRHx/OPDBRLx) to the 16-bit MPG
output data register (upper/lower) (OPDUR/OPDLR) is continued for waveform generation,
but no waveform is output to the OPT5 to OPT0 pins.
Figure 21.5-25 shows the DTTI circuit block diagram and Figure 21.5-26 shows the DTTI
circuit timing diagram when D[1:0] is set to "0b00".
■ DTTI Circuit Block Diagram
DTTI PIN
DTIE
D1
D0
NRSL
MN702-00009-2v0-E
Figure 21.5-25 DTTI Circuit Block Diagram
INPUT ENANLE OR
DISABLE SELECTOR
N-CYCLE DELAY
CIRCUIT
NOISE CANCELLATION
SELECTOR
DTTI INTERRURT AND
CONTROL GENERATOR
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 21 MULTI-PULSE GENERATOR
N can be 4, 8, 16, 32
depending on the
setting of D[1:0] bits
in the noise cancellation
control register (NCCR).
DTIF
DTISP
21.5 Operations
417

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