Fujitsu 8FX Hardware Manual page 325

MB95630H Series
● If the external clock stops while the clock supervisor counter is operating, and it restarts
after the second rising edge of the time-base timer interval selected, CMCEN is set to "0"
after the external clock restarts.
Selected time-base
timer interval
Main/Sub-oscillation clock
CMCEN
Internal counter
CMDR register
● With the clock supervisor counter running, if the external clock stops, CMCEN is set to "0"
when a falling edge of the time-base timer interval selected is detected after the second
rising edge of the same interval. The counter is cleared at the same falling edge.
Selected time-base
timer interval
Main/Sub-oscillation clock
CMCEN
Internal counter
CMDR register
MN702-00009-2v0-E
Figure 17.5-1 Clock Supervisor Counter Operation 1
0
Figure 17.5-2 Clock Supervisor Counter Operation 2
0
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 17 CLOCK SUPERVISOR COUNTER
17.5 Notes on Using Clock Supervisor
0
0
Counter
5 6
6
5 0
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