Notes On Using Watchdog Timer - Fujitsu 8FX Hardware Manual

MB95630H Series
8.5

Notes on Using Watchdog Timer

This section provides notes on using the watchdog timer.
■ Notes on Using Watchdog Timer
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Stopping the watchdog timer
Software watchdog timer
Once activated, the watchdog timer cannot be stopped until a reset is generated.
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Selecting the count clock
Software watchdog timer
The count clock switch bits (WDTC:CS[1:0], CSP) can be modified only when the watchdog
control bits (WDTC:WTE[3:0]) are set to "0b0101" after the activation of the watchdog timer.
The count clock switch bits cannot be set by a bit manipulation instruction. Moreover, the bit
settings should not be changed once the timer is activated.
In subclock mode or sub-CR clock mode, the time-base timer does not operate because the
main clock, the main CR clock, or the main CR PLL clock stops oscillating.
In order to make the watchdog timer operate in subclock mode or sub-CR clock mode, it is
necessary to select the watch prescaler as the count clock beforehand and set WDTC:CS[1:0],
CSP to "0b100" or "0b110" or "0bXX1" (X = 0 or 1).
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Clearing the watchdog timer
Clearing the timer (time-base timer, watch prescaler or sub-CR timer) used as the count clock
of the watchdog timer also clears the counter of the watchdog timer.
The counter of the watchdog timer is cleared when the watchdog timer transits to sleep mode,
stop mode, or watch mode, except in the case of activating hardware watchdog timer whose
operation in standby mode has been enabled.
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Programming precaution
When creating a program in which the watchdog timer is cleared repeatedly in the main loop,
set the processing time of the main loop including the interrupt processing time to the
minimum watchdog timer interval time or shorter.
●
Hardware watchdog timer (operation in standby mode has been enabled)
The hardware watchdog timer does not stop in stop mode, sleep mode, time-base timer mode
or watch mode. Therefore, the hardware watchdog timer is not cleared by the CPU even if the
internal clock stops. (in stop mode, sleep mode, time-base timer mode or watch mode).
Regularly release the device from standby mode and clear the watchdog timer. However,
depending on the setting of the oscillation stabilization wait time setting register, a watchdog
reset may be generated after the CPU wakes up from stop mode in subclock mode or sub-CR
clock mode.
Take account of the setting of the subclock stabilization wait time when selecting the subclock.
MN702-00009-2v0-E
CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER
FUJITSU SEMICONDUCTOR LIMITED
8.5 Notes on Using Watchdog Timer
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