Fujitsu 8FX Hardware Manual page 419

MB95630H Series
■ OPDUR and OPDLR Write Timing Diagram (OPS[2:0] = 0b000)
Figure 21.5-6 OPDUR and OPDLR Write Timing Diagram (OPS[2:0] = 0b000)
OPS[2:0]
RDA[2:0]
0b101
(OPDUR)
ODBR0W
ODBR1W
OPDBRL0[0]
OPDBRL1[0]
WTO
OP00
■ Signal Flow Diagram for Reload Timer Underflow by Setting OPS[2:0] = 0b001
Figure 21.5-7 Signal Flow Diagram for Reload Timer Underflow (OPS[2:0] = 0b001)
16-BIT RELOAD TIMER
OPDBRH0/OPDBRL0
WRITE SIGNAL
SNI2 to
Pin
SNI0
The 16-bit reload timer can be started by TIN input or a software trigger. The write signal is
controlled by the 16-bit reload timer underflow.
MN702-00009-2v0-E
TIN TIN0O
TOUT
WTIN0
ODBR0W
POSITION
WTIN1
DETECTION
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 21 MULTI-PULSE GENERATOR
0b000
0b001
DATA WRITE CONTROL UNIT
21.5 Operations
Pin TI1
TIN0
WRITE
WTO
TIMING
OUTPUT
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