Fujitsu 8FX Hardware Manual page 530

2
CHAPTER 24 I C BUS INTERFACE
24.6 Operations and Setting Procedure Example
Figure 24.6-3 Timing Diagram with No Interrupt Generated with IBCR0n:ALF = 1
SCLn pin or SDAn pin at "L" level
SCLn pin
SDAn pin
2
I C operation enabled (ICCRn:EN = 1)
Master mode set (IBCR1n:MSS = 1)
Arbitration lost detection bit
(IBCR0n:ALF = 1)
Bus busy (IBSRn:BB)
Interrupt (IBCR1n:INT)
508 FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
"L"
"L"
1
0
0
MN702-00009-2v0-E