Overview - Fujitsu 8FX Hardware Manual

CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR

23.1 Overview

23.1 Overview
The UART/SIO dedicated baud rate generator generates the baud rate for the
UART/SIO.
The generator consists of the UART/SIO dedicated baud rate generator
prescaler select register ch. n (PSSRn) and UART/SIO dedicated baud rate
generator baud rate setting register ch. n (BRSRn).
The number of pins and that of channels of the UART/SIO dedicated baud rate generator vary
among products. For details, refer to the device data sheet.
In this chapter, "n" in a pin name and a register abbreviation represents the channel number.
For details of pin names, register names and register abbreviations of a product, refer to the
device data sheet.
■ Block Diagram of UART/SIO Dedicated Baud Rate Generator
Figure 23.1-1 Block Diagram of UART/SIO Dedicated Baud Rate Generator
MCLK
(Machine clock)
Prescaler
■ Input Clock
The UART/SIO dedicated baud rate generator uses the output clock from the prescaler or the
machine clock as its input clock.
■ Output Clock
The UART/SIO dedicated baud rate generator supplies its clock to the UART/SIO.
486
Baud rate generator
PSS[1:0]
CLK
MCLK/2
MCLK/4
MCLK/8
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
BRS[7:0]
BRCLK
8-bit
downcounter
UART/SIO
1/4
MN702-00009-2v0-E