Fujitsu 8FX Hardware Manual page 466

CHAPTER 21 MULTI-PULSE GENERATOR
21.6 Registers
[bit2] SEE2: SNI2 enable bit
This bit enables or disables the edge detection on the SNI2 pin.
Set this bit before setting the CMPE bit in the input control register (upper) (IPCUR) to "0".
bit2
Writing "0"
Writing "1"
[bit1] SEE1: SNI1 enable bit
This bit enables or disables the edge detection on the SNI1 pin.
Set this bit before setting the CMPE bit in the input control register (upper) (IPCUR) to "0".
bit1
Writing "0"
Writing "1"
[bit0] SEE0: SNI0 enable bit
This bit enables or disables the edge detection on the SNI0 pin.
Set this bit before setting the CMPE bit in the input control register (upper) (IPCUR) to "0".
bit0
Writing "0"
Writing "1"
444
Disables the edge detection on the SNI2 pin.
Enables the edge detection on the SNI2 pin.
Disables the edge detection on the SNI1 pin.
Enables the edge detection on the SNI1 pin.
Disables the edge detection on the SNI0 pin.
Enables the edge detection on the SNI0 pin.
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
Details
Details
Details
MN702-00009-2v0-E