Fujitsu 8FX Hardware Manual page 255

MB95630H Series
Serial clock cycle#
Serial clock
Serial input
(LIN bus)
FRE
(RXE = 1)
LBD
(RXE = 0)
Receive interrupt generated when RXE = 1
● LIN bus timing
Previous serial clock
LIN
bus
(SIN)
RXE
LBD
(IRQ)
LBIE
TII0 input
(LSYN)
IRQ(TII0)
RDRF
(IRQ)
RIE
RDR read
by CPU
Enable receive
interrupts
LIN break starts
LIN break detected, interrupt generated
IRQ clear by CPU (LBD
IRQ (8/16-bit composite timer)
IRQ clear: input capture of 8/16-bit composite timer count starts
IRQ clear: Baud rate calculated and set
MN702-00009-2v0-E
Figure 14.6-8 LIN-UART Operation in LIN Slave Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 14.6-9 LIN Bus Timing and LIN-UART Signals
No clock
(Calculation frame)
8/16-bit composite timer count
0)
IRQ (8/16-bit composite timer)
LBIE disabled
Reception enabled
Falling edge of start bit
1 byte of reception data saved to RDR
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14 LIN-UART
14.6 Operations of LIN-UART and LIN-UART
Setting Procedure Example
Receive interrupt generated when RXE = 0
Newly calculated serial clock
RDR read by CPU
233