Uart/Sio Serial Mode Control Register 1 Ch. N (Smc1N) - Fujitsu 8FX Hardware Manual

MB95630H Series
22.7.1 UART/SIO Serial Mode Control Register 1 ch. n
(SMC1n)
The UART/SIO serial mode control register 1 ch. n (SMC1n) controls the UART/
SIO operation mode. The register is used to set the serial data direction
(endian), parity and its polarity, stop bit length, operation mode (clock
synchronous mode / clock asynchronous mode), data length, and serial clock.
■ Register Configuration
bit 7
Field BDS
Attribute R/W
Initial value 0
■ Register Functions
[bit7] BDS: Serial data direction control bit
This bit controls the serial data direction (endian).
bit7
Writing "0"
Writing "1"
[bit6] PEN: Parity control bit
This bit enables or disables the parity in clock asynchronous mode (UART).
bit6
Writing "0"
Writing "1"
[bit5] TDP: Parity polarity control bit
This bit controls the even/odd parity.
bit5
Writing "0"
Writing "1"
[bit4] SBL: Stop bit length control bit
This bit controls the stop bit length in clock asynchronous mode (UART).
bit4
Writing "0"
Writing "1"
Note: The setting of this bit is only valid for transmission operation in clock asynchronous mode (UART). In
a receive operation, regardless of the setting of this bit, the UART/SIO completes the receive operation
when detecting a stop bit (one bit), and sets the receive data register full flag bit (SSRn:RDRF) to "1".
MN702-00009-2v0-E
6 5
PEN TDP
R/W R/W
0 0
Transmission or reception starts from the LSB in the UART/SIO serial input/output data register
ch. n (RDRn/TDRn).
Transmission or reception starts from the MSB in the UART/SIO serial input/output data register
ch. n (RDRn/TDRn).
Disables the parity.
Enables the parity.
Selects the even parity.
Selects the odd parity.
1 bit
2 bits
FUJITSU SEMICONDUCTOR LIMITED
4 3
SBL CBL1
R/W R/W
0 0
Details
Details
Details
Details
CHAPTER 22 UART/SIO
22.7 Registers
2 1
CBL0 CKS
R/W R/W
0 0
0
MD
R/W
0
477