Time-Base Timer Control Register (Tbtc) - Fujitsu 8FX Hardware Manual

CHAPTER 7 TIME-BASE TIMER
7.5 Register
7.5.1

Time-base Timer Control Register (TBTC)

The time-base timer control register (TBTC) selects the interval time, clears the
counter, controls interrupts and checks the status of the time-base timer.
■ Register Configuration
bit 7
Field TBIF
Attribute R/W
Initial value 0
■ Register Functions
[bit7] TBIF: Time-base timer interrupt request flag bit
This bit is set to "1" when the interval time selected by the time-base timer has elapsed.
When this bit and the time-base timer interrupt request enable bit (TBIE) are set to "1", an interrupt request is
output.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit7
Reading "0"
Reading "1"
Writing "0"
Writing "1"
[bit6] TBIE: Time-base timer interrupt request enable bit
This bit enables or disables output of interrupt requests to interrupt controller.
When this bit and the time-base timer interrupt request flag bit (TBIF) are set to "1", a time-base timer
interrupt request is output.
bit6
Writing "0"
Writing "1"
[bit5] Undefined bit
The read value is always "0". Writing a value to this bit has no effect on operation.
96
6 5
TBIE —
R/W —
0 0
Indicates that the interval time has not elapsed.
Indicates that the interval time has elapsed.
Clears this bit.
Has no effect on operation.
Disables the time-base timer interrupt request.
Enables the time-base timer interrupt request.
FUJITSU SEMICONDUCTOR LIMITED
4 3
TBC3 TBC2
R/W R/W
0 0
Details
Details
MB95630H Series
2 1
TBC1 TBC0
R/W R/W
0 0
MN702-00009-2v0-E
0
TCLR
W
0