Operations - Fujitsu 8FX Hardware Manual

MB95630H Series
17.3

Operations

This section describes the operations of the clock supervisor counter.
■ Clock Supervisor Counter
● Clock Supervisor Counter Operation 1
The clock supervisor counter is first enabled by the software (CMCEN = 1), and then the clock
supervisor counter operates with the time-base timer interval selected from eight options by the
TBTSEL[2:0] bits. Between two rising edges of the time-base timer interval selected, the
internal counter is clocked by the external clock.
The count clock of this module can be selected from the main oscillation clock and the
suboscillation clock.
Selected time-base
timer interval
Main/Sub-oscillation clock
CMCEN
Internal counter
CMDR register
● Clock Supervisor Counter Operation 2
The CMDR register is cleared when the CMCEN bit changes from "0" to "1".
Selected time-base
timer interval
Main/Sub-oscillation clock
CMCEN
Internal counter
CMDR register
MN702-00009-2v0-E
Figure 17.3-1 Clock Supervisor Counter Operation 1
0
Figure 17.3-2 Clock Supervisor Counter Operation 2
0
0
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 17 CLOCK SUPERVISOR COUNTER
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Clear
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17.3 Operations
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