8/16-Bit Ppg Timer N1/N0 Cycle Setup Buffer Register (Ppsn1/Ppsn0) - Fujitsu 8FX Hardware Manual

MB95630H Series
18.7.3 8/16-bit PPG timer n1/n0 Cycle Setup Buffer
Register (PPSn1/PPSn0)
The 8/16-bit PPG timer n1/n0 cycle setup buffer register (PPSn1/PPSn0) sets
the PPG output cycle.
■ Register Configuration
PPSn1
bit 7
Field PH7
Attribute R/W
Initial value 1
PPSn0
bit 7
Field PL7
Attribute R/W
Initial value 1
■ Register Functions
The PPSn1 and PPSn0 registers set the PPG output cycle.
• In 16-bit PPG mode, PPSn1 serves as the upper 8 bits, while PPSn0 serves as the lower 8
bits.
• In 16-bit PPG mode, write the upper bits before the lower bits. When only the upper bits are
written, the previously written value is reused in the next load.
• 8-bit mode: Cycle = max. 255 (0xFF)
• 16-bit mode: Cycle = max. 65535 (0xFFFF)
• PPSn1 and PPSn0 are initialized upon reset.
• Do not set the cycle to "0x00" or "0x01" when using the unit in 8-bit PPG independent
mode or 8-bit prescaler mode + 8-bit PPG mode.
• Do not set the cycle to "0x0000" or "0x0001" when using the unit in 16-bit PPG mode.
• If the cycle settings are modified during the operation, the modified settings will be
effective from the next PPG cycle.
MN702-00009-2v0-E
6 5
PH6 PH5
R/W R/W
1 1
6 5
PL6 PL5
R/W R/W
1 1
FUJITSU SEMICONDUCTOR LIMITED
4 3
PH4 PH3
R/W R/W
1 1
4 3
PL4 PL3
R/W R/W
1 1
Input clock cycle
Input clock cycle
CHAPTER 18 8/16-BIT PPG
18.7 Registers
2 1
PH2 PH1
R/W R/W
1 1
2 1
PL2 PL1
R/W R/W
1 1
0
PH0
R/W
1
0
PL0
R/W
1
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