Fujitsu 8FX Hardware Manual page 183

MB95630H Series
[bit6:4] C[2:0]: Count clock select bits
These bits select the count clock.
The count clock is generated by the prescaler. See "3.9 Operation of Prescaler".
During timer operation (Tn0CR1/Tn1CR1:STA = 1), the write access to these bits has no effect on operation
in timer operation.
The clock selection of Tn1CR0 (timer n1) is nullified in 16-bit operation.
These bits cannot be set to "0b111" when the PWC function or input capture function is used. An attempt to
write "0b111" with the PWC function or input capture function in use resets the bits to "0b000". The bits are
also reset to "0b000" if the timer enters the input capture operation mode with the bits set to "0b111".
When these bits are set to "0b110", the count clock from the time-base timer is used as the count clock.
Depending on the settings of the SYCC register, the count clock from the time-base timer can be generated
from the main clock, the main CR clock, or the main CR PLL clock. In the case of using the count clock
from the time-base timer as the count clock, resetting the time-base timer by writing "1" to the time-base
timer clear bit in the time-base timer control register (TBTC:TCLR) affects the count time.
bit6:4
Writing "000"
Writing "001"
Writing "010"
Writing "011"
Writing "100"
Writing "101"
Writing "110"
Writing "111"
*: The value to be used as the count clock depends on the settings of the SCS[2:0] bits in the SYCC register.
MN702-00009-2v0-E
(MCLK: machine clock, F
1 MCLK
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
7 6
F /2 , F /2 or F
CH CRH MCRPLL
External clock
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 11 8/16-BIT COMPOSITE TIMER
Details
: main clock, F
CH
F : main CR PLL clock)
MCRPLL
6
/2 *
11.14 Registers
: main CR clock,
CRH
161