Fujitsu 8FX Hardware Manual page 323

MB95630H Series
[bit0] CMCEN: Counter enable bit
This bit enables or disables the clock supervisor counter.
Writing "0" to this bit stops the counter and clears the CMDR register to "0b00000000".
Writing "1" to this bit enables the counter. The counter starts counting when detecting the rising edge of the
time-base timer interval. It stops counting when detecting the second rising edge of the same interval.
This bit is automatically set to "0" when the counter stops.
bit0
Writing "0"
Writing "1"
Notes:
• Do not modify the CMCSEL bit when the CMCEN bit is "1".
• Do not modify the TBTSEL[2:0] bits when the CMCEN bit is "1".
MN702-00009-2v0-E
Disables the counter operation.
Enables the counter operation.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 17 CLOCK SUPERVISOR COUNTER
Details
17.4 Registers
301