Fujitsu 8FX Hardware Manual page 68

CHAPTER 3 CLOCK CONTROLLER
3.5 Operations in Low Power Consumption
Mode (Standby Mode)
■ Standby Mode State Transition Diagram (with Deep Standby Mode Enabled)
Figure 3.5-2 shows a standby mode state transition diagram (with deep standby mode enabled).
Figure 3.5-2 Standby Mode State Transition Diagram (with Deep Standby Mode Enabled)
Stop mode
(4)
Main clock/main CR clock/main CR PLL clock/
Sleep mode (Flash recovery wait time*)
(6)
Sleep mode (Flash recovery wait time*)
Time-base
timer mode
*: Flash memory recovery wait time (SCLK: source clock, MCLK: machine clock)
•
•
46
(3)
subclock/sub-CR clock
oscillation stabilization wait time
In main clock mode, main CR clock mode, or main CR PLL clock mode
Maximum: 10 SCLK + 150 µs + 6 MCLK
In subclock mode or sub-CR clock mode
Maximum: 2 SCLK + 150 µs + 6 MCLK
FUJITSU SEMICONDUCTOR LIMITED
Power on
Reset state A reset occurs in any state.
<1>
Main CR clock
oscillation stabilization
wait time
+
sub-CR clock
oscillation stabilization
wait time
Normal
(RUN) state
Sleep mode (Flash recovery wait time*)
(5) (1)
(2)
Sleep mode (Flash recovery wait time*)
MB95630H Series
(7)
Watch mode
(8)
Sleep mode
MN702-00009-2v0-E