Fujitsu 8FX Hardware Manual page 115

MB95630H Series
■ Operation Examples of Time-base Timer
Figure 7.4-2 shows examples of operations under the following conditions:
1. A power-on reset is generated.
2. The device transits to the sleep mode during the operation of the interval timer function in
main clock mode, main CR clock mode or main CR PLL clock mode.
3. The device transits to the stop mode in main clock mode, main CR clock mode or main CR
PLL clock mode.
4. A request is generated to clear the counter.
If the device transits to the time-base timer mode, the same operations are executed as those
executed when the device transits to the sleep mode.
In stop mode in which the clock mode is subclock mode, sub-CR clock mode, main clock
mode, main CR clock mode or main CR PLL clock mode, the timer operation stops because it
is cleared and the main clock stops.
Counter value
(count down)
0xFFFFFF
Count value detected in
TBTC:TBC[3:0]
0x000000
stabilization
1) Power-on reset
TBIF bit
TBIE bit
2) SLP bit
(STBC register)
3) STP bit
(STBC register)
• When setting the interval time select bits in time-base timer control register (TBTC:TBC[3:0]) to "0b0011" (2
• TBTC:TBC[3:0]
• TBTC:TCLR
• TBTC:TBIF
• TBTC:TBIE
• STBC:SLP
• STBC:STP
MN702-00009-2v0-E
Figure 7.4-2 Operations of Time-base Timer
Oscillation
wait time
: Interval time select bits in time-base timer control register
: Time-base timer initialization bit in time-base timer control register
: Time-base timer interrupt request flag bit in time-base timer control register
: Time-base timer interrupt request enable bit in time-base timer control register
: Sleep bit in standby control register
: Stop bit in standby control register
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 7 TIME-BASE TIMER
7.4 Operations and Setting Procedure
Interval cycle
(TBTC:TBC[3:0] = 0b0011)
Cleared by
to stop mode
4) Counter cleared
(TBTC:TCLR = 1)
Cleared in interrupt
Cleared at
service routine
interval setting
Sleep
Sleep mode released by
time-base timer interrupt
Stop mode released by external interrupt
Example
transition
Oscillation
stabilization wait time
Stop
16
2/F )
CH
93