Fujitsu 8FX Hardware Manual page 298

CHAPTER 15 8/10-BIT A/D CONVERTER
15.6 Registers
[bit3] ADIE: Interrupt request enable bit
This bit enables or disables outputting the interrupt request to the interrupt controller.
When both this bit and the interrupt request flag bit (ADC1: ADI) have been set to "1", an interrupt request is
output.
bit3
Writing "0"
Writing "1"
[bit2] EXT: Continuous start enable bit
This bit selects whether to start the A/D conversion function with the software, or to continuously start the
A/D conversion function whenever a rising edge of the input clock is detected.
bit2
Writing "0"
Writing "1"
[bit1:0] CKDIV[1:0]: Clock select bits
These bits select the clock (CKIN) to be used for A/D conversion. The input clock is generated by the
prescaler. See "3.9 Operation of Prescaler" for details.
The sampling time varies according to the clock selected by these bits.
Modify these bits according to operating conditions (voltage and frequency).
bit1:0
Writing "00"
Writing "01"
Writing "10"
Writing "11"
Note: Modify these bits only when the A/D converter has stopped operating.
276
Disables outputting the interrupt request.
Enables outputting the interrupt request.
Starts the A/D conversion function with the AD bit in the ADC1 register.
Continuously start the A/D conversion function according to the clock selected by the ADCK bit
in the ADC2 register.
1 MCLK
MCLK/2
MCLK/4
MCLK/8
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
Details
Details
Details
(MCLK: machine clock)
MN702-00009-2v0-E