Fujitsu 8FX Hardware Manual page 267

MB95630H Series
[bit4] CL: Data length select bit
This bit specifies the data length to be transmitted and received. This bit is fixed at "1" in operating mode 2
and operating mode 3.
bit4
Writing "0"
Writing "1"
[bit3] AD: Address/data format select bit
This bit specifies the data format for the frame to be transmitted and received in multiprocessor mode
(operating mode 1). Write a value to this bit in master mode; read this bit in slave mode. The operation in
master mode is as follows.
The value for the last received data format is read.
bit3
Writing "0"
Writing "1"
Note: See "14.8 Notes on Using LIN-UART" for the usage of this bit.
[bit2] CRE: Receive error flag clear bit
This bit clears the FRE, ORE, and PE flags in serial status register (SSR).
bit2
Read access
Writing "0"
Writing "1"
[bit1] RXE: Receive operation enable bit
This bits enables or disables the receive operation of the LIN-UART.
The LIN synch break detection in operating mode 3 is not affected by the setting of this bit.
bit1
Writing "0"
Writing "1"
Note: When data frame reception is disabled (RXE = 0) while it is in progress, the reception halts
immediately. In this case, the integrity of data is not guaranteed.
[bit0] TXE: Transmit operation enable bit
This bits enables or disables the transmit operation of the LIN-UART.
bit0
Writing "0"
Writing "1"
Note: When data frame transmission is disabled (TXE = 0) while it is in progress, the transmission halts
immediately. In this case, the integrity of data is not guaranteed.
MN702-00009-2v0-E
7 bits
8 bits
Sets the data frame as the data format.
Sets the address data frame as the data format.
The read value is always "0".
Has no effect on operation.
Clears the receive error flags (SSR:FRE, ORE, PE).
Disables data frame reception.
Enables data frame reception.
Disables data frame transmission.
Enables data frame transmission.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14 LIN-UART
Details
Details
Details
Details
Details
14.7 Registers
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