Fujitsu 8FX Hardware Manual page 61

MB95630H Series
Table 3.4-1 Clock Mode State Transition Table (1 / 2)
Current
Next State
State
<1> Reset state Main CR clock
(1)
Sub-CR clock
(2)
(3)
Main CR clock/
Main CR PLL
clock
Subclock
(4)
(5)
Main clock
(6)
(7)
Main CR clock/
Main CR PLL
clock
Main clock
(8)
(9)
Sub-CR clock Same as (1) and (2)
(10)
(11)
Subclock
(12)
MN702-00009-2v0-E
After a reset, the device waits for the main CR clock oscillation stabilization wait time
and the sub-CR clock oscillation stabilization wait time to elapse and transits to main
CR clock mode. Even if that reset is a watchdog reset, software reset or external reset
caused in any clock mode, the device waits for the sub-CR clock oscillation
stabilization wait time and the main CR clock oscillation stabilization wait time to
elapse.
The device transits to sub-CR clock mode when the clock mode select bits in the
system clock control register (SYCC:SCS[2:0]) are set to "0b100".
However, when the sub-CR has been stopped according to the setting of the sub-CR
clock oscillation enable bit in the system clock control register 2 (SYCC2:SCRE), the
device waits for the sub-CR clock oscillation stabilization wait time to elapse before
transiting to sub-CR clock mode. In other words, when the sub-CR clock oscillation is
enabled in advance, and the sub-CR clock oscillation stabilization bit in the system
clock control register 2 (SYCC2:SCRDY) is "1", the device transits to sub-CR clock
mode immediately after the clock mode select bits (SYCC:SCS[2:0]) are set to
"0b100".
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b000", the device transits to subclock mode after waiting for the subclock
oscillation stabilization wait time.
When the subclock oscillation is enabled by the setting of the subclock oscillation
enable bit in the system clock control register 2 (SYCC2:SOSCE), and the subclock
oscillation stabilization bit in the system clock control register 2 (SYCC2:SRDY) is
"1", the device transits to subclock mode immediately after the clock mode select bits
(SYCC:SCS[2:0]) are set to "0b000".
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b010", the device transits to main clock mode after waiting for the main
clock oscillation stabilization wait time.
When the main clock oscillation is enabled by the setting of the main clock oscillation
enable bit in the system clock control register 2 (SYCC2:MOSCE), and the main clock
oscillation stabilization bit in the system clock control register 2 (SYCC2:MRDY) is
"1", the device transits to main clock mode immediately after the clock mode select
bits (SYCC:SCS[2:0]) are set to "0b010".
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b110", the device transits to main CR clock mode after waiting for the
main CR clock oscillation stabilization wait time. When the main CR clock oscillation
is enabled by the setting of the main CR clock oscillation enable bit in the system
clock control register 2 (SYCC2:MCRE), and the main CR clock oscillation
stabilization bit in the system clock control register 2 (SYCC2:MCRDY) is "1", the
device transits to main CR clock mode immediately after the clock mode select bits
(SYCC:SCS[2:0]) are set to "0b110".
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b111", the device transits to main CR PLL clock mode after waiting for the
main CR PLL clock oscillation stabilization wait time. When the main CR PLL clock
oscillation is enabled by the setting of the main CR PLL clock enable bit in the PLL
control register (PLLC:MPEN), and the main CR PLL clock oscillation stabilization
bit in the PLL control register (PLLC:MPRDY) is "1", the device transits to main CR
PLL clock mode immediately after the clock mode select bits (SYCC:SCS[2:0]) are
set to "0b111".
Same as (3) and (4)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 3 CLOCK CONTROLLER
Description
3.4 Clock Modes
39