Sleep Mode - Fujitsu 8FX Hardware Manual

CHAPTER 3 CLOCK CONTROLLER
3.5 Operations in Low Power Consumption
Mode (Standby Mode)
3.5.2

Sleep Mode

In sleep mode, the operations of the CPU and watchdog timer are stopped.
■ Operations in Sleep Mode
In sleep mode, the CPU and the operating clock for the watchdog timer are stopped. The CPU
retains the contents of registers and RAM existing at the point immediately before the device
transits to sleep mode and stops; however, all peripheral functions except the watchdog timer
continue their operations.
In the case of hardware watchdog timer, if it is enabled in standby mode by the non-volatile
register function, in sleep mode, the sub-CR clock does not stop and the hardware watchdog
timer continues its operation. For details, see "CHAPTER 27 NON-VOLATILE REGISTER
(NVR) INTERFACE".
● Transition to sleep mode
Writing "1" to the sleep bit in the standby control register (STBC:SLP) causes the device to
enter sleep mode.
● Release from sleep mode
A reset or an interrupt from a peripheral function releases the device from sleep mode.
With the deep standby mode control bit (STBC2:DSTBYX) set to "0", even after a reset occurs
or an interrupt is generated by a peripheral function, the device continues operating in sleep
mode until the Flash recovery wait time elapses.
However, if a program is being executed on the RAM, no Flash recovery wait time occurs.
48 FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
MN702-00009-2v0-E