16-Bit Mpg Input Control Register (Upper) (Ipcur) - Fujitsu 8FX Hardware Manual

MB95630H Series
21.6.5.1 16-bit MPG Input Control Register (Upper)
(IPCUR)
The 16-bit MPG input control register (upper) (IPCUR) controls PPG edge
synchronization and the compare operation.
■ Register Configuration
bit 7
Field WTS1
Attribute R/W
Initial value 0
■ Register Functions
[bit7:6] WTS[1:0]: PPG edge synchronization select bits
These bits select which edge of the next PPG signal is to be synchronized with the write timing.
bit7:6
Writing "00"
Writing "01"
Writing "10"
Writing "11"
[bit5] CPIF: Compare interrupt request flag bit
This bit is the compare interrupt request flag for the compare circuit. When the RDA[2:0] bits are compared
with the CPD[2:0] bits and they match, this bit is set to "1".
With the compare interrupt request already enabled (CPIE = 1), when this bit is set to "1", a compare
interrupt is generated.
Writing "0" to this bit clears it. Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit5
Reading "0"
Reading "1"
Writing "0"
Writing "1"
[bit4] CPIE: Compare interrupt enable bit
This bit enables or disables the compare interrupt.
When this bit is set to "1", and the compare interrupt request flag bit (CPIF) is also set to "1", a compare
interrupt is generated.
bit4
Writing "0"
Writing "1"
MN702-00009-2v0-E
6 5
WTS0 CPIF
R/W R/W
0 0
No edge synchronization
Rising edge
Falling edge
Both edges
Indicates that no compare interrupt request has been generated.
Indicates that a compare interrupt request has been generated.
Clears this bit.
Has no effect on operation.
Disables the compare interrupt.
Enables the compare interrupt.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 21 MULTI-PULSE GENERATOR
4 3
CPIE CPD2
R/W R/W
0 0
Details
Details
Details
21.6 Registers
2 1
CPD1 CPD0
R/W R/W
0 0
0
CMPE
R/W
0
441