Fujitsu 8FX Hardware Manual page 229

MB95630H Series
A receive interrupt request is made if the receive interrupt has been enabled (SSR:RIE = 1)
when one of the above flag bits is "1".
RDRF flag is automatically cleared to "0" if the LIN-UART receive data register (RDR) is
read. All of the error flags are cleared to "0" if "1" is written to the receive error flag clear bit
(CRE) in the LIN-UART serial control register (SCR).
● LIN synch break interrupts
In operating mode 3, the LIN synch break interrupt functions when the LIN-UART performs
LIN slave operation.
The LIN synch break detection flag bit (LBD) in the LIN-UART extended status control
register (ESCR) is set to "1" when the internal data bus (serial input) is "0" for 11 bits or
longer. The LIN synch break interrupt and the LBD flag are cleared by writing "0" to the LBD
flag. The LBD flag must be cleared before the 8/16-bit composite timer interrupt is generated
within the LIN synch field.
To detect a LIN synch break, disable the reception (SCR:RXE = 0).
■ Transmit Interrupts
Table 14.4-2 shows the control bit and interrupt source of the transmit interrupt.
Table 14.4-2 Interrupt Control Bit and Interrupt Source of Transmit Interrupt
Interrupt Operating mode
Flag
request flag
register
bit
❍
TDRE SSR
❍: Bit to be used
● Transmit interrupts
The transmit data register empty flag bit (TDRE) in the LIN-UART serial status register (SSR)
is set to "1" when the transmit data is transferred from the LIN-UART transmit data register
(TDR) to the transmit shift register, and data transmission starts. In this case, if the transmit
interrupt has been enabled (SSR:TIE = 1), a transmit interrupt request is made.
Note:
Since the initial value of the TDRE bit is "1" after a hardware reset/software reset, if the
TIE bit is set to "1" after a hardware reset/software reset, an interrupt is generated
immediately. The TDRE bit is cleared only by writing data to the LIN-UART transmit data
register (TDR).
MN702-00009-2v0-E
Interrupt source
0 1 2 3
❍ ❍ ❍ Transmit register is empty
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14 LIN-UART
Interrupt source Interrupt request flag
enable bit
SSR:TIE Write transmit data
14.4 Interrupts
clear
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