Fujitsu 8FX Hardware Manual page 490

CHAPTER 22 UART/SIO
22.6 Operations and Setting Procedure Example
● Transmission in clock asynchronous mode (UART)
Use UART/SIO serial mode control register 1 ch. n (SMC1n) to select the serial data direction
(endian), parity/non-parity, parity polarity, stop bit length, character bit length, and clock.
Either of the following two procedures can be used to initiate the transmission process:
• Set the transmission operation enable bit (TXE) to "1", and then write transmit data to the
UART/SIO serial output data register ch. n (TDRn) to start transmission.
• Write transmit data to the UART/SIO serial output data register ch. n (TDRn), and then set
the transmission operation enable bit (TXE) to "1" to start transmission.
Transmit data is written to the TDRn register after it is checked that the transmit data register
empty flag bit (TDRE) set to "1".
When the transmit data is written to the TDRn register, the TDRE bit is cleared to "0".
The transmit data is transferred from the TDRn register to the transmission shift register, and
the TDRE bit is set to "1".
When the transmit interrupt enable bit (TIE) contains "1", a transmit interrupt occurs if the
TDRE bit is set to "1". This allows the next piece of transmit data to be written to the TDRn
register by interrupt handling.
To detect the completion of serial transmission by transmit interrupt, set the transmission
completion interrupt enable bits as follows: TEIE = 0, TCIE = 1. Upon completion of
transmission, the transmission completion flag bit (SSRn:TCPL) is set to "1" and a transmit
interrupt occurs.
The TCPL bit, and the TDRE bit in consecutive data transmission are set at the position which
the transmission of the last bit was completed (it varies depending on the data length, parity
enable, or stop bit length setting), as shown in Figure 22.6-6.
Note that modifying UART/SIO serial mode control register 1 ch. n (SMC1n) during
transmission may result in unpredictable operation.
Figure 22.6-6 Transmission in Clock Asynchronous Mode (UART)
UOn D5
TCPL
TDRE
Transmit
interrupt
468
D6 D7 P
When the STOP bit length is set to 1 bit
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
SP SP
When the STOP bit length is set to 2 bits
MN702-00009-2v0-E