Standby Control Register 2 (Stbc2) - Fujitsu 8FX Hardware Manual

CHAPTER 3 CLOCK CONTROLLER
3.3 Registers
3.3.6

Standby Control Register 2 (STBC2)

The standby control register 2 (STBC2) controls the deep standby mode.
■ Register Configuration
bit 7
Field —
Attribute —
Initial value 0
■ Register Functions
[bit7:1] Undefined bits
Their read values are always "0". Writing values to these bits has no effect on operation.
[bit0] DSTBYX: Deep standby mode control bit
This bit makes the device transit to deep standby mode by setting the Flash memory to the low-power state in
standby mode.
bit0
Writing "0"
Writing "1"
Notes:
• Waking up the device from deep standby mode and waking up the device from the
normal standby mode have the following difference.
In main clock mode, main CR clock
mode, or main CR PLL clock mode
In subclock mode or sub-CR clock
mode
• Refer to "■ ELECTRICAL CHARACTERISTICS" in the device data sheet for the
difference between the deep standby mode and the normal standby mode in power
consumption.
• Do not make the device transit to deep standby mode when a Flash command
sequence (except read/reset) has been invoked.
36
6 5
— —
— —
0 0
Sets the Flash memory to the low-power state when the device enters standby mode according to
the setting of the standby control register (STBC). (deep standby mode)
Keeps the Flash memory at the normal state when the device enters standby mode according to
the setting of the standby control register (STBC). (normal standby mode)
FUJITSU SEMICONDUCTOR LIMITED
4 3
— —
— —
0 0
Details
Maximum time required to wake up the device from deep
standby mode
(SCLK: source clock, MCLK: machine clock)
(10 SCLK + 150 µs + 6 MCLK) +
(2 SCLK + 150 µs + 6 MCLK)
MB95630H Series
2 1
— — DSTBYX
— —
0 0
time required to wake up the
device from normal standby mode
time required to wake up the
+
device from normal standby mode
MN702-00009-2v0-E
0
R/W
0