Fujitsu 8FX Hardware Manual page 415

MB95630H Series
■ 16-bit MPG Output Data Register (Upper/Lower) (OPDUR/OPDLR)
The content of the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR) is sent
from the 16-bit MPG output data buffer register (upper/lower) (OPDBRHB and OPDBRLB -
OPDBRH0 and OPDBRL0) according to the write timing signal (WTO) generated by the data
write control unit, and the OPTx output waveform is updated. Moreover, the output level can
be compulsorily fixed by the DTTI pin input.
Table 21.5-1 16-bit MPG Output Data Register (Upper/Lower) (OPDUR/OPDLR)
OPx1,OPx0 Setting
OPx1,OPx0 = 0,0
OPx1,OPx0 = 0,1
OPx1,OPx0 = 1,0
OPx1,OPx0 = 1,1
The OPTx output waveform timing diagram is shown in Figure 21.5-2 and the operation is
explained in following sections.
■ OPTx Output Waveform Timing Diagram (WTS[1:0] = 0b00)
Figure 21.5-2 OPTx Output Waveform Timing Diagram (WTS[1:0] = 0b00)
WTO
OPx1,
OPx0
0b00
(OPDUR,
OPDLR)
PPG
OPTx
"L" Output
MN702-00009-2v0-E
"L" level
16-bit PPG timer output
16-bit PPG timer inverted output
"H" level
0b01
PPG Output
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 21 MULTI-PULSE GENERATOR
OPTx Output
0b11
PPG Inverted Output
"H" Output
21.5 Operations
0b10
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