Flash Memory Status Register 4 (Fsr4) - Fujitsu 8FX Hardware Manual

CHAPTER 26 DUAL OPERATION FLASH MEMORY
26.8 Registers
26.8.5

Flash Memory Status Register 4 (FSR4)

This section describes of the flash memory status register 4 (FSR4).
■ Register Configuration
bit 7
Field —
Attribute —
Initial value 0
■ Register Functions
[bit7] Undefined bit
The read value of this bit is always "0". Writing a value to this bit has no effect on operation.
[bit6] CEREND: CEREND interrupt request flag bit
This bit indicates the completion of Flash memory chip erase.
The CEREND bit is set to "1" upon completion of the Flash memory automatic algorithm.
When the CEREND bit is set to "0" after Flash memory chip erase is completed, further Flash memory
programming/erasing is disabled. Writing a reset command can make the Flash memory return to the normal
command state.
When Flash memory chip erase fails (FSR3:HANG = 1), this bit is cleared to "0".
Writing "0" to this bit clears it.
Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit6
Reading "0"
Reading "1"
Writing "0"
Writing "1"
[bit5] CTIEN: CERTO interrupt enable bit
This bit enables or disables the generation of interrupt requests triggered by the failure of Flash memory chip
erase.
bit5
Writing "0"
Writing "1"
572
6 5
CEREND CTIEN
R/W R/W
0 0
Indicates that the device is in the command input wait state or Flash memory chip erase is in
progress.
Indicates that Flash memory chip erase has been completed.
Clears this bit.
Has no effect on operation.
Disables the interrupt request upon failure of Flash memory chip erase (FSR4:CERTO = 1).
Enables the interrupt request upon failure of Flash memory chip erase (FSR4:CERTO = 1).
FUJITSU SEMICONDUCTOR LIMITED
4 3
CERTO —
R/W —
0 0
Details
Details
MB95630H Series
2 1
— —
— —
0 0
MN702-00009-2v0-E
0
—
—
0