Fujitsu 8FX Hardware Manual page 371

MB95630H Series
[bit4] RTRG: Software retrigger enable bit
This bit enables or disables using the software retrigger function while the 16-bit PPG timer is in operation.
bit4
Writing "0"
Writing "1"
[bit3:1] CKS[2:0]: Operating clock select bits
These bits select the operating clock for the 16-bit PPG timer.
The operating clock is generated from the prescaler. For details, see "3.9 Operation of Prescaler".
bit3:1
Writing "000"
Writing "001"
Writing "010"
Writing "011"
Writing "100"
Writing "101"
Writing "110"
Writing "111"
Note: In subclock mode or sub-CR clock mode, since the time-base timer stops operating, setting CKS[2:0]
to "0b110" or "0b111" is prohibited.
[bit0] PGMS: PPG output mask enable bit
This bit is used to mask the PPGn output to a specific level regardless of the mode setting (PCNTHn:MDSE),
period setting (PCSRHn, PCSRLn), and duty setting (PDUTHn, PDUTLn).
Writing "0" to this bit disables the PPGn output mask function.
Writing "1" to this bit enables the PPGn output mask function. When the PPGn output polarity setting is set
to "normal" (PCNTLn:OSEL = 0), the output is always masked to "L".
When the polarity setting is se to "inverted" (PCNTLn:OSEL = 1), the PPGn output is always masked to "H".
bit0
Writing "0"
Writing "1"
MN702-00009-2v0-E
Disables using the software retrigger function while the 16-bit PPG timer is in operation.
Enables using the software retrigger function while the 16-bit PPG timer is in operation.
(MCLK: machine clock, F
F : main CR clock, F
CRH
1 MCLK
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
7 6
F /2 or F /2 or F
CH CRH MCRPLL
8 7
F /2 or F /2 or F
CH CRH MCRPLL
Disables the PPGn output mask function.
Enables the PPGn output mask function.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 19 16-BIT PPG TIMER
Details
Details
: main clock,
CH
: main CR PLL clock)
MCRPLL
6
/2
7
/2
Details
19.7 Registers
349