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LAVENDER-
Subboard
Documentation
©
Fujitsu Microelectronics Europe GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag, Germany

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Summary of Contents for Fujitsu LAVENDER

  • Page 1 LAVENDER- Subboard Documentation © Fujitsu Microelectronics Europe GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag, Germany...
  • Page 2 History Revision Date Comment V1.0 06.03.01 New Document...
  • Page 3: No Liability For Consequential Damages

    However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
  • Page 4: Important Notice

    This Starterkit contains an evaluation board, documentation and software on a CD-ROM. For documentation or software updates, please refer to our web site www.fujitsu-fme.com Fujitsu reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice. 06.03.01 V1.0...
  • Page 5 Introduction The LAVENDER-Subboard is a low cost multifunctional evaluation board for Fujitsu graphic device controller Lavender. It can be used with CREMSON-Starterkit CPU-Modul only for software development and testing as a simple target board. The board allows the designer immediately to start the software development before his own final target system is available.
  • Page 6 JP201 Lavender 0 Lavender 1 Mode1-0 Lavender 2 Lavender 3 Lavender can also act as a 16Bit device from MCU’s point of view. The data mode can be set by Jumper JP203. JP203 Description 32 Bit data mode Mode2 16 Bit data mode It is possible to invert the RDY signal (Mode3 = 1).
  • Page 7 Test mode Test Run mode 3.5 Reset Pin (JP212) The Jumper JP212 determines the Lavender Reset Pin. It can be connected directly with the Reset of the VGC, or with a port of the MCU, to execute a software Reset. JP212...
  • Page 8 JP306 Description Video flag from ext. Video active flag video decoder from ext. video decoder JP307 Description Video clock output from Video Scaler Clock SAA7111A 3.7 SBP Bus JP209 Description SPB needs pull-up for ON (closed) operation SPB_BUS OFF (open) SPB no operation 3.8 Header for Debug Signals CCFL Signals (JP208)
  • Page 9 ULB_CS - Chip select • ULB_DREQ - DMA request signal • ULB_DACK - DMA acknowledge signal For more information please look at the Hardware Manual of the Lavender graphic controller and the Data Sheet of the Video Input Processor SAA7111A.
  • Page 10: Schematics And Drawings

    Schematics and Drawings...
  • Page 15 JP504 ULB_WRX0 ULB_WRX1 BUS_DIS_D16 BUS_DIS_D17 DIS_VREF ULB_WRX2 ULB_WRX3 BUS_DIS_D18 BUS_DIS_D19 CGND ULB_CLK ULB_CS BUS_DIS_D20 BUS_DIS_D21 ULB_DREQ ULB_DACK BUS_DIS_D22 BUS_DIS_D23 HD-DSUB-BU-15POL CGND HEADER 2x19 BUS_DIS_D[0:23] BUS_DIS_D[0:23] HEADER 2x5 Title LAVENDER-SUBBOARD, FUJ24B Size Document Number STECKER Date: Monday, February 05, 2001 Sheet...