Topology 2A: Init; Figure 37. Routing Illustration For Init; Figure 38. Voltage Translation Of Init; Table 17. Layout Recommendations For Init# (Topology 2A) - Intel Pentium 4 Design Manual

System Bus Routing
5.4.1.3

Topology 2A: INIT#

Table 17. Layout Recommendations for INIT# (Topology 2A)

Trace Zo
60 Ω

Figure 37. Routing Illustration for INIT#

VCC_CPU
Level shifting is required for the INIT# signal to the FWH in order to meet the input logic levels of
the FWH. Figure 38 illustrates one method of implementing this level shifting.

Figure 38. Voltage Translation of INIT#

INIT# from
74
Trace L1
Spacing
7 mil 2" max
Processor
R
PU
L3
4.7k
ICH2
® ®
Intel Pentium 4 Processor / Intel
L2 L3
10" max 3" max
ICH2
L4 L1
12V
4.7k
®
850 Chipset Family Platform Design Guide
L4 L5
300 Ω 5%
17" max 3" max
VCC_FWH
300 Ω ±5%
L5
L2
FWH
Voltage
Translator
Topo2a_Route
Volt_Trans_INIT
R
Rpu