In Circuit Lpc Flash Bios Programming; Stackup Requirement; Overview - Intel VC820 - Desktop Board Motherboard Design Manual

System Manufacturing
5.1 In Circuit FWH Flash BIOS Programming
All cycles destined for the FWH Flash BIOS appear on PCI. The ICH hub interface to PCI Bridge
puts all processor boot cycles out on PCI (before sending them out on the FWH Flash BIOS
interface to the FWH Flash BIOS). If the ICH is set for subtractive decode, these boot cycles can be
accepted by a positive decode agent out on PCI. The enables the ability to boot from of a PCI card
that positively decodes these memory cycles. To boot from a PCI card it is necessary to keep the
ICH in subtractive decode mode. If a PCI boot card is inserted and the ICH is programmed for
positive decode, there will be two devices positively decoding the same cycle. In systems with the
82380AB (ISA bridge), it is also necessary to keep the NOGO signal asserted when booting from a
PCI ROM. Note that it is not possible to boot from a ROM behind the 82380AB. Once you have
booted from the PCI card, you could potentially program the FWH Flash BIOS in circuit and
program the ICH CMOS.
5.2 FWH Flash BIOS Vpp Design Guidelines
The Vpp pin on the FWH Flash BIOS is used for programming the flash cells. The FWH Flash
BIOS supports Vpp of 3.3V or 12V. If Vpp is 12V, the flash cells will program about 50% faster
than at 3.3V. However, the FWH Flash BIOS only supports 12V Vpp for 80 hours. The 12V Vpp
would be useful in a programmer environment that is typically an event that occurs very
infrequently (much less than 80 hours). The VPP pin MUST be tied to 3.3V on the motherboard.
5.3

Stackup Requirement

5.3.1

Overview

®
The Intel
dimension (previously, typically 7 mil) is required because of the signaling environment used for
Direct RDRAM, AGP 2.0 and hub interface. The RDRAM Channel is designed for 28 Ω and
mismatched impedance will cause signal reflections which will reduce voltage and timing margins.
For example, with a 2X clock at 400 MHz operation, which equals a 1.25 ns sampling window,
only 100 ps is allotted for total channel timing error. Channel error results not only from PCB
impedance, but also PCB and Z
28 Ω impedance.
®
Intel 820 Chipset Design Guide
820 chipset platform requires a board stackup with a 4.5 mil prepreg. This change in
process variation. Therefore, it is critical to attain the required
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System Manufacturing
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