Bandwidth Summary - Intel VC820 - Desktop Board Motherboard Design Manual

Introduction
I/O Controller Hub (ICH)
The I/O Controller Hub provides the I/O subsystem with access to the rest of the system.
Additionally, it integrates many I/O functions. The ICH integrates the following functions:
•
Upstream hub interface for access to the MCH
•
2 channel Ultra ATA/66 Bus Master IDE controller
•
USB controller
•
I/O APIC
•
SMBus controller
•
FWH interface (FWH Flash BIOS)
•
LPC interface
•
AC'97 2.1 interface
•
PCI 2.2 interface
•
Integrated System Management Controller
•
Alert on LAN*
The ICH also contains the arbitration and buffering necessary to ensure efficient utilization of these
interfaces. Refer to
interfaces.
ISA Bridge (82380AB)
For legacy needs, ISA support is an optional feature of the Intel
require ISA support can benefit from the enhancements of the Intel
designs are not burdened with the complexity and cost of the ISA subsystem.
®
The Intel
bridge. The bridge is a PCI to ISA bridge and resides on the PCI bus of the ICH.
1.3.2

Bandwidth Summary

Table 1-1
®
Table 1-1. Intel 820 Chipset Platform Bandwidth Summary
Interface
Processor Bus
RDRAM
AGP 2.0
Hub Interface
PCI 2.2
1-4
Chapter 2, "Layout/Routing Guidelines"
820 chipset platform with optional ISA support takes advantage of the 82380AB ISA
provides a summary of the bandwidth requirements for the Intel
Clock Speed Samples
(MHz) Per Clock
133
266/300/356/400
66
66
33
for more information on these
®
Data Rate
(Mega-samples/s)
1 133
2 533/600/711/800
4 266
4 266
1 33
820 chipset. Implementations that
®
820 chipset while "ISA-less"
®
820 chipset.
Data Width Bandwidth
(Bytes) (MB/s)
8 1066
2 1066/1200/1422/1600
4 1066
1 266
4 133
®
Intel 820 Chipset Design Guide