Related Manuals for Intel Pentium III
Summary of Contents for Intel Pentium III
- Page 1 ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide June 2001 Document Number 249658-001...
- Page 2 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
-
Page 3: Table Of Contents
Dual Processor Power Requirements ..............5-3 5.3.1 Voltage Tolerance ................5-3 5.3.2 Multiple Voltages ................5-4 5.3.3 Voltage Sequencing ................5-4 Meeting Power Requirements ................5-4 5.4.1 Supplying Voltage ................5-4 ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... - Page 4 Host Interface AGTL Bus and AGTL Signals .............8-1 CMOS (Non-AGTL) Signals ................8-2 TAP/ITP Checklist for 370-Pin Socket Processors ..........8-3 Miscellaneous Checklist for 370-Pin Socket Processors ........8-4 ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide...
- Page 5 Example Dual Processor THERMTRIP# Workaround Circuit ......6-2 Voltage Range Comparison ................7-2 Active Voltage Positioning Operating Parameters ..........7-3 Package Comparisons ..................7-4 Electrical Keying Mechanism ................7-5 SE Clocking Implementation ................7-8 ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide...
- Page 6 THERMTRIP# Timing Requirements ..............6-1 Pin Differences List ....................7-4 Signalling Parameter Comparisons..............7-6 AGTL Signals .....................8-1 CMOS Signals....................8-2 TAP/ITP Signals....................8-3 Clock Signals .....................8-4 Miscellaneous Signals..................8-4 Power Signals ....................8-5 ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide...
- Page 7 Revision History Revision Draft/Changes Date -001 Initial Version June 2001 ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide...
- Page 8 This page intentionally left blank...
-
Page 9: Design Guide Introduction
EMI design impacts and system bus decoupling. ® Please note that this document describes the design recommendations that are driven by the Intel ® Pentium III Processor with 512KB L2 Cache’s specifications. -
Page 10: Conventions And Terminology
1. Unless otherwise noted, this reference material can be found on the Intel Developer’s Website located at http:// developer.intel.com. 2. For a complete listing of Intel® Pentium® III processor reference material, please refer to the Intel Developer’s Website at http:/ /developer.intel.com/design/PentiumIII/ Conventions and Terminology For this document, the following terminology applies. -
Page 11: State Of The Data
State of the Data The data contained within this document are based on near-production validation testing and silicon characterization. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... - Page 12 This page intentionally left blank...
-
Page 13: General Design Considerations
General Design Considerations ® ® This section documents motherboard layout and routing guidelines for Intel Pentium III Processor with 512KB L2 Cache platforms. This section does not discuss the functional aspects of any bus, or the layout guidelines for an add-in device. -
Page 14: Socket 370 Component Keepout
EMI Pads 1 . 022" Max. Height Off MB 1 . 54 1 . 83 . 672 . 210 All dimensions are minimum unless otherwise specified ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 15: Socket 370 Volumetric Keepout
Figure 2-3. Socket 370 Volumetric Keepout ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... - Page 16 This page intentionally left blank...
-
Page 17: Processor Host Bus Design
® ® Component timings for the Intel Pentium III Processor with 512KB L2 Cache are available in the Intel ® Pentium III Processor with 512KB L2 Cache Datasheet. Please contact your chipset vendor for documentation concerning the chipset component timing. -
Page 18: General Topology And Layout Guidelines
The PCB skew specification is based on the results of extensive simulations at Intel. The T value is based on Intel’s experience with systems that use previous generations of processors. Table 3-3. System Bus Timing Parameters... -
Page 19: System Bus T-Topology
3.25 3.75 3.25 3.75 1.75 Table 3-6. Component Values for T Topology Reference Value Tolerance R1 (on chip) 68Ω R2 (on chip) 68Ω 68Ω 68Ω ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 20: Terminator-Less T Topology
Please Note: Intel will not be validating the terminator-less T topology design. This design is based on extensive simulation results that have been performed by Intel. It is provided as a reference for designs seeking to not require a terminator when the system is operating with one processor. Intel recommends that any implementation of this topology be simulated and validated carefully. -
Page 21: Wired-Or Signal Considerations
T topology or the terminator-less T topology. Please note that the incorporation of Wired-OR termination is optional. Intel has not seen any failures on systems which do not implement the Wired-OR termination recommendations. Therefore, systems which are already in the latter phases of design may wish to forego implementing these recommendations until an opportunity presents itself to incorporate them. -
Page 22: Wired-Or Termination Topology
Choosing a value at the lower end of the range (around 100Ω) will provide optimal dampening but has a larger impact on the signal flight times. Intel recommends a value of 150Ω +/- 10% as a reasonable trade-off between dampening and flight time. -
Page 23: Simulation Methodology
Intel recommends running simulations at the device pads for signal quality and at the device pins for timing analysis. However, simulation results at the device pins may be used later to correlate simulation performance against actual system measurements. -
Page 24: Minimizing Crosstalk
Although CMOS signals are slow, they may still have speed path problems. This is especially true for APIC clock and APIC data. Try to avoid long routes. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 25: Undershoot/Overshoot Requirements
However, the implementation is not flexible in system and execution signal connections. Intel will use an ITP for internal debug and system validation and recommends that all system designs include a debug port. -
Page 26: Simple Terminations
Refer to BCLK system requirements documentation BCLK, BCLK# for proper termination values and routing requirements DBRESET#, BSEN#, Figure 3-4a DBINST# Figure 3-4. Simple Terminations ® ® 3-10 Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 27: Tck Termination, Dp System
The flight time of the RESET# signal from the closest RESET# processor must be added to the arrival time of BCLK at Figure 3-7 the Debug Port. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 3-11... -
Page 28: Prdyx# Signal Termination
Figure 3-6. PRDYx# Signal Termination Figure 3-7. RESET# Signal Termination ® ® 3-12 Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 29: Debug Port Termination Requirement
TMS, TDO, TDI, POWERON, DBRESET#, 1" max from debug port to RT AND 12" max from debug port to Figure 3-4 BSEN#, processor DBINST#, PREQx# ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 3-13... -
Page 30: Jtag Signals Tdi/Tdo For Processor Only
Figure 3-10 illustrate possible bypass configurations with a three pin jumper and a four- pin jumper. Figure 3-8. JTAG Signals TDI/TDO for Processor Only ® ® 3-14 Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 31: Tdo 3-Pin Jumper Bypass
Figure 3-9. TDO 3-Pin Jumper Bypass Figure 3-10. 4-Pin Jumper Bypass ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 3-15... - Page 32 This page intentionally left blank...
-
Page 33: Clocking
The host bus clock signals are critical signals in a platform design. The signal integrity and timing of these signals should be carefully evaluated and simulated. The following sections provide host clocking ® ® recommendations for the two supported Intel Pentium III Processor with 512KB L2 Cache clocking methodologies: single-ended clocking and differential clocking. -
Page 34: Single Ended Host Bus Clocking Routing
Driver Processor 1 Chipset Debug port ® ® The clocking requirements and timing information for the Intel Pentium III Processor with 512KB L2 ® ® Cache can be found in the Intel Pentium III Processor with 512KB L2 Cache Datasheet. For additional information about the timing and clocking requirements of the chipset component, please contact your chipset vendor for the appropriate documentation. -
Page 35: Single Ended Clocking Topology - Cpu
Figure 4-3. Single Ended Clocking Topology - Chipset Clock Driver Chipset Zo = 60 ohm Zo = 60 ohm ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 36: Clkref Filter Implementation
The CLKREF filter should be placed as close as possible (less that 1.0 inch) to the processor’s CLKREF pin. Figure 4-4. CLKREF Filter Implementation PGA370 Vcc2.5 CLKREF ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 37: Single-Ended Clocking Bsel[1:0] Implementation
4.2.2 Single-Ended Clocking BSEL[1:0] Implementation ® ® In an Intel Pentium III Processor with 512KB L2 Cache platform that is using single-ended (SE) clocking or a clock source that does not support the VTT_PWRGD protocol, the normal BSEL frequency selection process will not work. Since the clock generator is not compatible with dynamic BSEL assertions, all BSEL[1:0] signals should not be connected together. -
Page 38: Differential Clocking Topology
• Minimize stubs to passive components. • Clock to chipset is 1 inch longer than the clock to CPU (to compensate for CPU package load). ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 39: Differential Clocking Bsel[1:0] Implementation
Debug Port pins. Clock trace lengths may be adjusted to center the recovery of BPM[5:0]# and RESET# at the Debug Port within the ITP receiver setup an hold window. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 40: Clock Driver Decoupling And Power Delivery
However, since proper decoupling and noise-free power delivery are critical to the clock driver’s operation, Intel encourages system implementors to carefully follow the chipset and clock driver vendor’s recommendations in these areas. An incorrect implementation of these circuits can easily cripple a clock driver’s ability to produce reliable clock signals and lead to system instability. -
Page 41: Power
Power ® The intent of this section is to familiarize the reader with the processor power requirements for an Intel ® Pentium III Processor with 512KB L2 Cache dual processor platform, and to show simulation model and power implementation techniques. Only specific power distribution and control issues pertaining to ®... -
Page 42: Ideal Processor Power Supply Scheme
® ® regulator. However, due to the load-line characteristics specified by the Intel Pentium Processor with 512KB L2 Cache, Intel recommends that separate power planes be utilized. This configuration of voltage regulators is shown in Figure 5-2. Figure 5-2. Power Distribution for a DP System Motherboard... -
Page 43: Dual Processor Power Requirements
(13) SENSE 1Ω Dual Processor Power Requirements ® ® This section describes the issues related to supplying power to an Intel Pentium III Processor with ® ® 512KB L2 Cache. For detailed electrical specifications, please refer to the Intel Pentium III Processor with 512KB L2 Cache Datasheet. -
Page 44: Multiple Voltages
Meeting Power Requirements ® ® Intel recommends using VRM 8.5 compliant modules or embedded regulator designs for Intel Pentium III Processor with 512KB L2 Cache dual processor system board designs. The system board designer should properly place high frequency and bulk decoupling capacitors as needed between the voltage regulator and processor to ensure voltage fluctuations remain in specification. -
Page 45: Decoupling Technology And Transient Response
5.4.2.1 Location of High Frequency Decoupling ® ® A system designer for Intel Pentium III Processors with 512KB L2 Cache should properly design for high frequency decoupling. High frequency decoupling should be placed as close to the power pins of the processor as physically possible. -
Page 46: Recommendations
5.04 A Recommendations ® ® Intel recommends using simulation to design and verify Intel Pentium III Processor with 512KB L2 Cache dual processor based systems. With the estimates provided in the previous section, a model of the power source, and the model of the processor, system developers can begin analog modeling. The following sections contain Intel's design recommendations. -
Page 47: Decoupling Guidelines
V , and one should be connected between V and ground. If this circuit is far from the processor, add a 0.1-uF capacitor for decoupling. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 48: Processor Pll Filter Recommendations
Processor PLL Filter Recommendations It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements. A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated, decoupled power source for the internal PLL. -
Page 49: Pll Power Low Pass Filter Response
DC voltage drop from VCC to PLL1 should be < 60mV, which in practice implies series R < 2Ω; also means pass band (from DC to 1Hz) attenuation < 0.5dB for VCC = 1.1V, and < 0.35dB for VCC = 1.5V. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... - Page 50 This page intentionally left blank...
-
Page 51: Thermals
1/2 Nominal Vcc 5.0 seconds 1/2 Nominal Vtt 5.0 seconds THERMTRIP# Erratum Intel has identified an issue with THERMTRIP# which may incorrectly assert during de-assertion of ® ® RESET# at nominal operating temperatures in Intel Pentium III Processors with 512KB L2 Cache (CPUID 06B1h). -
Page 52: Example Dual Processor Thermtrip# Workaround Circuit
® Please consult the Pentium III Processor Specification Update for additional information on this issue. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 53: Processor Migration Considerations
III Processor with 512KB L2 Cache requires a VRM 8.5 compliant VRM for its power supply. Compliance with the following subsections is required for proper processor operation. This new VRM specification contains several features needed to meet the Intel® Pentium® III Processor with 512KB L2 Cache's operating requirements. -
Page 54: Active Voltage Positioning
VID3 VID2 VID1 VID0 1.05 1.075 1.10 1.125 1.15 1.175 1.20 1.225 1.25 1.275 1.30 ® ® Intel Pentium No Core 1.35 Processor with 1.375 512KB L2 Cache 1.40 1.425 Voltage Range 1.45 1.475 1.50 1.525 1.55 1.575 1.60 1.625 ®... -
Page 55: Vrm 8.5 Modules
The module keepout area has also changed in the new design. Volumetrically, the module is smaller than the VRM 8.4 module design. The new connector is now longer, but results in a smaller overall board area. Please refer to the VRM 8.5 DC-DC Converter Design Guidelines from Intel for more information. Package Changes (FC-PGA2) ®... -
Page 56: Pinout Changes
® ® further from the socket, so larger heatsink clips may be needed. Please refer to the Intel Pentium Processor with 512KB L2 Cache Datasheet for more detailed information about the FC-PGA2 mechanical design. Figure 7-3. Package Comparisons FC-PGA FC-PGA... -
Page 57: Electrical Keying Mechanism
An AGTL+ only processor will be held in reset if it is placed in ® ® ® ® an Intel Pentium III Processor with 512KB L2 Cache platform. The Intel Pentium III Processor (CPUID 068xh) with AGTL Capability works in both platforms and is keyed accordingly. Figure 7-4 shows ®... -
Page 58: Dual Processor Specific Pin Recommendations
III Processor with 512KB L2 Cache compatible system. It is used to prevent incompatible AGTL+ only processors from functioning in the system. An AGTL+ only processor placed in the system will be held in reset by this pin. Intel ®... -
Page 59: Host Bus Layout Changes
® AGTL+ only processor platform terminator will not work in an Intel Pentium III Processor with 512KB L2 Cache platform because of the pin differences. Please consult the Intel Developer Website for vendor information. Host Bus Layout Changes ® ®... -
Page 60: Power On Sequence
7.9.1 Power On Sequence ® ® The power on sequence for the Intel Pentium III Processor with 512KB L2 Cache has changed as ® ® compared to AGTL+ only processors. The Intel Pentium III Processor with 512KB L2 Cache now receives VTT_PWRGD as part of the sequence to indicate that the voltage regulator can latch the ®... -
Page 61: Picclk Voltage Change
Dynamic BSEL selection could be used in a legacy or single-ended clock driver system. A complex circuit to delay power delivery to the clock drivers and chipsets is needed to allow for dynamic BSEL operation. Intel will not be pursuing such a design recommendation. 7.10 PICCLK Voltage Change The voltage level for the PICCLK signal has changed to 2.0 volts. - Page 62 This page intentionally left blank...
-
Page 63: System Design Checklist
This checklist highlights design considerations that should be reviewed prior to manufacturing a ® ® motherboard that implements an Intel Pentium III Processor with 512KB L2 Cache system design. This is not a complete list and does not guarantee that a design will function properly. Besides the items in the following text, refer to the most recent version of the design guide for more detailed instructions on designing a motherboard. -
Page 64: Cmos (Non-Agtl) Signals
Connect to interrupt control logic and second CPU and pull up through ~330 Ω to LINT0/INTR VccCMOS. For boards supporting preproduction processors, this pin must be connected to frequency selection circuitry. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 65: Tap/Itp Checklist For 370-Pin Socket Processors
TAP/ITP Checklist for 370-Pin Socket Processors There are several mechanical, electrical, and functional constraints on the debug port which must be ® ® followed, please see the Intel Pentium III Processor with 512KB L2 Cache Datasheet, along with Chapter 3 of this document for details. -
Page 66: Miscellaneous Checklist For 370-Pin Socket Processors
THERMDN Thermal diode cathode. Connect to thermal sensor device. THERMDP Thermal diode anode. Connect to thermal sensor device. 68 Ω 1% pull-down to GND. RTTCTRL ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... -
Page 67: Power Signals
The following pins must be left as no-connects: AK30, AL1, E21, F10, L33, N33, Reserved N35, Q33, Q35, Q37, R2, W35, X2, Y1, Z36. ® ® Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide... - Page 68 This page intentionally left blank...