Pci Configuration 2 Register (Pcicfg2) 0Xd03C - Toshiba TX49 TMPR4937 Manual

10.4.13 PCI Configuration 2 Register (PCICFG2)
The following fields correspond to the following registers:
Max. Latency field → Max_Lat Register of the PCI Configuration Space
Min. Grant field → Min_Gnt Register of the PCI Configuration Space
Interrupt Pin field → Interrupt Pin Register of the PCI Configuration Space
Interrupt Line field → Interrupt Line Register of the PCI Configuration Space
This register cannot be accessed when the PCI Controller is in the Satellite mode.
31
ML
R/L
0x0A
15
IP
R/L
0x01
Bits Mnemonic Field Name
31:24 ML Maximum
Latency
23:16 MG Minimum Grant
15:8 IP Interrupt Pin
7:0 IL Interrupt Line
24 23
8 7
Max_Lat (Maximum Latency) (Default: 0x0A)
00h: Does not use this register to determine PCI Bus priority.
01h-FFh: Specifies the time interval for requesting bus ownership.
In units of 250 ns, assuming the PCICLK is 33 MHz.
It is possible to change the maximum latency by loading data from
Configuration EEPROM during initialization.
Min_Gnt (Minimum Grant) (Default: 0x02)
00h: Is not used to calculate the latency timer value.
01h-FFh: Sets the time required for Burst transfer.
In units of 250 ns, assuming the PCICLK is 33 MHz.
It is possible to change this value by loading data from Configuration
EEPROM during initialization.
Interrupt Pin (Default: 0x01)
Valid values: 00 - 04h
00h: Do not use interrupt signals.
01h: Use Interrupt signal INTA*
02h: Use Interrupt signal INTB*
03h: Use Interrupt signal INTC*
04h: Use Interrupt signal INTD*
05h - FFh: Reserved
It is possible to change this value by loading data from Configuration
EEPROM during initialization.
When using either the REQ[2]* signal or the PIO signal to report an
interrupt to an external device as the PCI device, please use EEPROM to
set the connection with that device.
Interrupt Line (Default: 0x00)
This is a readable/writable 8-bit register. The software uses this register to
indicate information such as the interrupt signal connection information.
Operation of the TX4937 is not affected.
Figure 10.4.11 PCI Configuration 2 Register
10-38
Chapter 10 PCI Controller
0xD03C
MG
R/L
0x02
IL
R/W
0x00
Description
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
R/L
R/L
R/L
R/W