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12.3 Detailed Explanation
12.3.1
Overview
The TX4937 has an on-chip 3-channel 32-bit timer/counter. Each channel supports the following
modes.
(1) Interval Timer Mode (Timer 0, 1, 2)
This mode periodically generates interrupts.
(2) Pulse Generator Mode (Timer 0, 1)
This is the pulse signal output mode.
(3) Watchdog Timer Mode (Timer 2)
This mode is used to monitor system abnormalities.
12.3.2
Counter Clock
The clock used for counting can be set to a frequency that is 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, or
1/256 of the internal clock (IMBUSCLK) frequency, or can be selected from nine counter input signal
(TCLK) types. Divide Register n (TMCCDRn) and the Counter Clock Select bit (TMTCRn.CCS) are
used to select the counter clock. In this situation, IMBUSCLK is the internal clock signal which is the
G-Bus clock divided by 2. See "Chapter 6 Clocks" for more information.
The counter input signal (TCLK) is used by three channels. Using TCLK makes it possible to count
external events. The External Clock Edge bit (TMTCRn.ECES) can be used to select the clock
rising/falling count.
Set the TCLK clock frequency to 45% or less of IMBUSCLK (TCLK = 27 MHz or less when
IMBUSCLK = 60 MHz). The following tables shows example count times when using 60 MHz or 66
MHz IMBUSCLK.
Table 12.3.1 Divide Value and Count (IMBUSCLK = 60 MHz)
Divide
TMCCDRn.
Rate
CCD
2
000
4
001
8
010
16
011
32
100
64
101
128
110
256
111
Counter Clock
Resolution (ns)
Frequency (Hz)
30.0 M
15.0 M
7.5 M
3.75 M
1.9 M
937.5 K
1066.67
468.8 K
2133.33
234.4 K
4266.67
12-3
Chapter 12 Timer/Counter
Max. Set Time
TMCPRAn Value
(sec.)
33.33
143.17
66.67
286.33
133.33
572.66
266.67
1145.32
533.33
2290.65
4581.30
9162.60
18325.20
for 1 sec.
30000000
15000000
7500000
3750000
1875000
937500
468750
234375
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