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– Only one channel performs single transfer
(1) Single transfer performed with only one channel
Perform either (a) or (b) to prevent a malfunction.
(2) Single transfer performed with one channel and burst transfer
Perform (b) to prevent a malfunction.
– Two or more channels perform single transfer
(3) Single transfer (performed with two to four channels)
Perform (a) to prevent a malfunction.
(4) Single transfer performed with two to three channels and burst transfer
Perform (a) to prevent a malfunction. For the channel used for burst transfer, set the same offset to
DMSARn and DMDARn, or set 1 to DMCCRn.USEXFSZ. (Set the on-chip FIFO to be shared
with multiple DMA channels by which no data remains in FIFO.)
In dual address burst transfer, when 0 is set to the transfer size mode bit and the offset value is
different between source address and destination address, data may remain in FIFO. (See 8.3.8.2
Burst Transfer During Dual address Transfer.) When a bus error occurs during single transfer for
which workaround (a) is performed, data is erased if it remains in FIFO during burst transfer. This
occurs because FIFO is reset due to a bus error. Since DMAC does not detect data erasing, you
need to set FIFO to contain no data.
Chapter 23 Notes on Use of TMPR4937
23-5
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