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Rev 1.1 Manual
23. Notes on Use of TMPR4938
23.1 Notes on External Bus Controller
23.2 Notes on DMA Controller
23-1
23.3 Note on PCI Controller
23.4 Notes on Serial I/O Port
23.5 Notes on Ether Controller
23-9
Modified line 2 of the introduction of Appendix A, TX49/H3
Core Supplement
A-1
Please refer to the "64-bit TX System RISC TX49/H3 Core
Architecture User's Manual" for more information regarding
the TX49/H3 Core.
TMPR4937 Revision History
Changes and Additions to Rev 1.1
23.1 Notes on TX49/H3 Core
23.2
Notes on External Bus Controller
23.3
Notes on DMA Controller
23.4
Note on PCI Controller
23.5
Notes on Serial I/O Port
23.6
Notes on Ether Controller
23.4 Note on PCI Controller
The section "Restriction when Initiator Write by PDMAC and
Target Read conflict" is added.
Please refer to the
"64-bit TX System RISC TX49/H2,
TX49/H3, TX49/H4 Core Architecture"
regarding the TX49/H3 Core.
8
for more information
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